Issued Patents All Time
Showing 25 most recent of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7863175 | Zero interface polysilicon to polysilicon gate for flash memory | Robert B. Ogle, Joong S. Jeon, Austin Frenkel | 2011-01-04 |
| 7713834 | Method of forming isolation regions for integrated circuits | Haihong Wang, Minh Van Ngo, Qi Xiang, Paul R. Besser, Ming-Ren Lin | 2010-05-11 |
| 7648886 | Shallow trench isolation process | Minh Van Ngo, Qi Xiang, Paul R. Besser, Ming-Ren Lin | 2010-01-19 |
| 7456062 | Method of forming a semiconductor device | William G. En, Thorsten Kammler, Paul R. Besser, Simon S. Chan | 2008-11-25 |
| 7422961 | Method of forming isolation regions for integrated circuits | Haihong Wang, Minh Van Ngo, Qi Xiang, Paul R. Besser, Ming-Ren Lin | 2008-09-09 |
| 7402485 | Method of forming a semiconductor device | William G. En, Thorsten Kammler, Scott Luning | 2008-07-22 |
| 7402207 | Method and apparatus for controlling the thickness of a selective epitaxial growth layer | Paul R. Besser, William G. En | 2008-07-22 |
| 7351638 | Scanning laser thermal annealing | Cyrus E. Tabery, Bin Yu, Qi Xiang, Robert B. Ogle | 2008-04-01 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same | Qi Xiang, Paul R. Besser, Minh Van Ngo, Haihong Wang | 2007-12-25 |
| 7298012 | Shallow junction semiconductor | Mario M. Pelella, William G. En, Witold P. Maszara | 2007-11-20 |
| 7256141 | Interface layer between dual polycrystalline silicon layers | Mark T. Ramsbey, Weidong Qian, Mark S. Chang | 2007-08-14 |
| 7241700 | Methods for post offset spacer clean for improved selective epitaxy silicon growth | William G. En, Scott Luning | 2007-07-10 |
| 7211489 | Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal | Qi Xiang, Robert B. Ogle, Cyrus E. Tabery, Bin Yu | 2007-05-01 |
| 7091097 | End-of-range defect minimization in semiconductor device | Qi Xiang, Cyrus E. Tabery, Bin Yu, Robert B. Ogle | 2006-08-15 |
| 7071065 | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication | Qi Xiang, Haihong Wang | 2006-07-04 |
| 7033916 | Shallow junction semiconductor and method for the fabrication thereof | Mario M. Pelella, William G. En, Witold P. Maszara | 2006-04-25 |
| 6966235 | Remote monitoring of critical parameters for calibration of manufacturing equipment and facilities | — | 2005-11-22 |
| 6967160 | Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness | Paul R. Besser, Simon S. Chan, Fred N. Hause | 2005-11-22 |
| 6962857 | Shallow trench isolation process using oxide deposition and anneal | Minh Van Ngo, Ming-Ren Lin, Haihong Wang, Qi Xiang, Jung-Suk Goo | 2005-11-08 |
| 6924182 | Strained silicon MOSFET having reduced leakage and method of its formation | Qi Xiang, Ming-Ren Lin, Minh Van Ngo, Haihong Wang | 2005-08-02 |
| 6921709 | Front side seal to prevent germanium outgassing | Haihong Wang, Qi Xiang | 2005-07-26 |
| 6905923 | Offset spacer process for forming N-type transistors | Haihong Wang, Qi Xiang | 2005-06-14 |
| 6902966 | Low-temperature post-dopant activation process | Bin Yu, Robert B. Ogle, Cyrus E. Tabery, Qi Xiang | 2005-06-07 |
| 6878592 | Selective epitaxy to improve silicidation | Paul R. Besser, Minh Van Ngo, Qi Xiang | 2005-04-12 |
| 6878559 | Measurement of lateral diffusion of diffused layers | Peter G. Borden, G. Jonathan Kluth | 2005-04-12 |