ZL

Zicheng Gary Ling

AM AMD: 24 patents #433 of 9,279Top 5%
Overall (All Time): #173,451 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10289784 Determination of clock path delays and implementation of a circuit design Chiao Kai Hwang, Nagaraj Savithri 2019-05-14
7724016 Characterizing circuit performance by separating device and interconnect impact on signal delay Xiao-Jie Yuan, Michael J. Hart, Steven P. Young 2010-05-25
7489152 Characterizing circuit performance by separating device and interconnect impact on signal delay Xiao-Jie Yuan, Michael J. Hart, Steven P. Young 2009-02-10
7109734 Characterizing circuit performance by separating device and interconnect impact on signal delay Xiao-Jie Yuan, Michael J. Hart, Steven P. Young 2006-09-19
7046026 Testing vias and contracts in integrated circuit Tai-An Chao, Shihcheng Hsueh 2006-05-16
6867580 Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits Jan Lodewijk de Jong 2005-03-15
6868537 Method of generating an IC mask using a reduced database Jonathan Ho, Xin Wu, Jan Lodewijk de Jong 2005-03-15
6842019 Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits Jan Lodewijk de Jong 2005-01-11
6784685 Testing vias and contacts in an integrated circuit Tai-An Chao, Shihcheng Hsueh 2004-08-31
6727710 Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits Jan Lodewijk de Jong 2004-04-27
6551870 Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer James Chiang 2003-04-22
6503765 Testing vias and contacts in integrated circuit fabrication Tai-An Chao, Shihcheng Hsueh 2003-01-07
6482573 Exposure correction based on reflective index for photolithographic process control Jayendra D. Bhakta, Weizhong Wang, Warren T. Yu, Eric Kent 2002-11-19
6479350 Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers Todd P. Lukanc, Raymond T. Lee 2002-11-12
6368762 Active mask exposure compensation of underlying nitride thickness variation to reduce critical dimension (CD) variation — 2002-04-09
6306702 Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length Ming-Yin Hao, Richard P. Rouse 2001-10-23
6287904 Two step mask process to eliminate gate end cap shortening Raymond T. Lee 2001-09-11
6265253 Aluminum disposable spacer to reduce mask count in CMOS transistor formation Todd P. Lukanc, Matthew S. Buynoski 2001-07-24
6221706 Aluminum disposable spacer to reduce mask count in CMOS transistor formation Todd P. Lukanc, Raymond T. Lee, Matthew S. Buynoski 2001-04-24
6218224 Nitride disposable spacer to reduce mask count in CMOS transistor formation Todd P. Lukanc, Raymond T. Lee 2001-04-17
6214655 Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation Raymond T. Lee 2001-04-10
6166558 Method for measuring gate length and drain/source gate overlap Chun Jiang, Wei Long, Yowjuang W. Liu 2000-12-26
6153455 Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer James Chiang 2000-11-28
6103563 Nitride disposable spacer to reduce mask count in CMOS transistor formation Todd P. Lukanc, Raymond T. Lee 2000-08-15