Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JH

Jonathan Ho — 15 Patents

AMD: 8 patents #1,570 of 9,280Top 20%
Google: 7 patents #3,814 of 22,993Top 20%
New York, NY: #1,234 of 20,192 inventorsTop 7%
New York: #9,821 of 115,490 inventorsTop 9%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Jonathan Ho has been granted 15 US patents while listed as an inventor at AMD. The first was granted in 2003 and the most recent in August 2025. Jonathan Ho ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Jonathan Ho in New York, NY, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12387096 Image-to-image mapping by iterative de-noising Chitwan Saharia, Mohammad Norouzi, William Chan, Huiwen Chang, David Fleet +2 more 2025-08-12
12277758 Generating videos using sequences of generative neural networks William Chan, Chitwan Saharia, Jay Ha Whang, Tim Salimans 2025-04-15
12165289 Image enhancement via iterative refinement based on machine learning models Chitwan Saharia, William Chan, Tim Salimans, David Fleet, Mohammad Norouzi 2024-12-10 $140,382,000
11978141 Generating images using sequences of generative neural networks Chitwan Saharia, William Chan, Mohammad Norouzi, Saurabh Saxena, Yi Li +2 more 2024-05-07 $112,500,000
11908180 Generating videos using sequences of generative neural networks William Chan, Chitwan Saharia, Jay Ha Whang, Tim Salimans 2024-02-20 $78,256,000
11769228 Image enhancement via iterative refinement based on machine learning models Chitwan Saharia, William Chan, Tim Salimans, David Fleet, Mohammad Norouzi 2023-09-26 $154,792,000
11756166 Image enhancement via iterative refinement based on machine learning models Chitwan Saharia, William Chan, Tim Salimans, David Fleet, Mohammad Norouzi 2023-09-12 $80,406,000
8384164 Interconnect structure 2013-02-26 $3,543,000
7951722 Double exposure semiconductor process for improved process margin 2011-05-31 $48,680,000
7765498 Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist Yan Wang, Xin Wu, Jane W. Sowards 2010-07-27 $4,055,000
7737020 Method of fabricating CMOS devices using fluid-based dielectric materials Hong-Tsz Pan 2010-06-15 $5,059,000
7673270 Method and apparatus for compensating an integrated circuit layout for mechanical stress effects Yan Wang, Nui Chong, Hong-Tsz Pan, Bang-Thu Nguyen, Qi Lin +4 more 2010-03-02 $5,003,000
6868537 Method of generating an IC mask using a reduced database Xin Wu, Zicheng Gary Ling, Jan Lodewijk de Jong 2005-03-15 $38,146,000
6569576 Reticle cover for preventing ESD damage Shih-Cheng Hsueh, Kevin T. Look 2003-05-27 $47,445,000
6569584 Methods and structures for protecting reticles from electrostatic damage Xin Wu 2003-05-27 $47,445,000