Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10134689 | Warpage compensation metal for wafer level packaging technology | Vivek Swaminathan Sridharan, Sriram Muthukumar | 2018-11-20 |
| 10032749 | Three-dimensional chip-to-wafer integration | Karthik Thambidurai, Viren Khandekar, Hien D. Nguyen | 2018-07-24 |
| 9704809 | Fan-out and heterogeneous packaging of electronic components | Khanh Tran, Arkadii V. Samoilov, Pirooz Parvarandeh | 2017-07-11 |
| 9472451 | Technique for wafer-level processing of QFN packages | Viren Khandekar, Karthik Thambidurai, Ahmad Ashrafzadeh, Hien D. Nguyen | 2016-10-18 |
| 9331048 | Bonded stacked wafers and methods of electroplating bonded stacked wafers | Quanbo Zou, Uppili Sridhar, Xuejun Ying | 2016-05-03 |
| 9324687 | Wafer-level passive device integration | Karthik Thambidurai, Peter R. Harper, Viren Khandekar | 2016-04-26 |
| 9219043 | Wafer-level package device having high-standoff peripheral solder bumps | Viren Khandekar, Hien D. Nguyen | 2015-12-22 |
| 9190391 | Three-dimensional chip-to-wafer integration | Karthik Thambidurai, Viren Khandekar, Hien D. Nguyen | 2015-11-17 |
| 9040386 | Method for varied topographic MEMS cap process | Xuejun Ying, Li Li, Brian S. Poarch | 2015-05-26 |
| 9000587 | Wafer-level thin chip integration | Vivek Swaminathan Sridharan | 2015-04-07 |
| 8970043 | Bonded stacked wafers and methods of electroplating bonded stacked wafers | Quanbo Zou, Uppili Sridhar, Xuejun Ying | 2015-03-03 |
| 8878350 | Semiconductor device having a buffer material and stiffener | Vivek Swaminathan Sridharan, Peter R. Harper | 2014-11-04 |
| 8860222 | Techniques for wafer-level processing of QFN packages | Viren Khandekar, Karthik Thambidurai, Ahmad Ashrafzadeh, Hien D. Nguyen | 2014-10-14 |
| 8124916 | Thermal processing of silicon wafers | Larry Puechner, David E. Billings | 2012-02-28 |
| RE40507 | Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG | Michael Whiteman | 2008-09-16 |
| 6828212 | Method of forming shallow trench isolation structure in a semiconductor device | Timothy Mark Barry, Nicolas Degors, Donald A. Erickson, Bradley J. Larsen | 2004-12-07 |
| 6824687 | Extraction of phenol from wastewater | Sunil Panditrao, Sanjeev Ram, Ajay Gami, James M. Hildreth | 2004-11-30 |
| 6709990 | Method for fabrication of a high capacitance interpoly dielectric | Mark Good | 2004-03-23 |
| 6495475 | Method for fabrication of a high capacitance interpoly dielectric | Mark Good | 2002-12-17 |
| 6489254 | Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG | Michael Whiteman | 2002-12-03 |
| 6291367 | Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer | — | 2001-09-18 |