Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10804233 | Wafer-level chip-scale package device having bump assemblies configured to maintain standoff height | Viren Khandekar, Vivek Swaminathan Sridharan | 2020-10-13 |
| 10304758 | Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active wafer | Ahmad Ashrafzadeh, Viresh Piyush Patel, Viren Khandekar | 2019-05-28 |
| 10032749 | Three-dimensional chip-to-wafer integration | Amit S. Kelkar, Viren Khandekar, Hien D. Nguyen | 2018-07-24 |
| 9806047 | Wafer level device and method with cantilever pillar structure | Peter R. Harper, Sriram Muthukumar, Arkadii V. Samoilov | 2017-10-31 |
| 9721912 | Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality | Viren Khandekar, Vivek Swaminathan Sridharan | 2017-08-01 |
| 9472451 | Technique for wafer-level processing of QFN packages | Viren Khandekar, Ahmad Ashrafzadeh, Amit S. Kelkar, Hien D. Nguyen | 2016-10-18 |
| 9425064 | Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages | Viren Khandekar, Tiao Zhou | 2016-08-23 |
| 9324687 | Wafer-level passive device integration | Amit S. Kelkar, Peter R. Harper, Viren Khandekar | 2016-04-26 |
| 9190391 | Three-dimensional chip-to-wafer integration | Amit S. Kelkar, Viren Khandekar, Hien D. Nguyen | 2015-11-17 |
| 9040408 | Techniques for wafer-level processing of QFN packages | Tiao Zhou, Joseph W. Serpiello, Md. Kaysar Rahim, Yong Li Xu, Viren Khandekar | 2015-05-26 |
| 8860222 | Techniques for wafer-level processing of QFN packages | Viren Khandekar, Ahmad Ashrafzadeh, Amit S. Kelkar, Hien D. Nguyen | 2014-10-14 |