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Home › Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby

Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby

US Patent 6329718 · Granted Dec 11, 2001

Estimated economic value: $6,262,000 ⓘ

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