Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7354839 | Gate structure and a transistor having asymmetric spacer elements and methods of forming the same | Andy Wei, Gert Burbach | 2008-04-08 |
| 6943067 | Three-dimensional integrated semiconductor devices | — | 2005-09-13 |
| 6362524 | Edge seal ring for copper damascene process and method for fabrication thereof | Richard C. Blish, II, Kurt Taylor | 2002-03-26 |
| 6319804 | Process to separate the doping of polygate and source drain regions in dual gate field effect transistors | Scott Luning | 2001-11-20 |
| 6159851 | Borderless vias with CVD barrier layer | Robert Chen, John A. Iacoponi | 2000-12-12 |
| 6096628 | Method of controlling effective channel length of semiconductor device by non-doping implantation at elevated energies | Jan Raebiger | 2000-08-01 |
| 5989963 | Method for obtaining a steep retrograde channel profile | Scott Luning, Jonathan Fewkes | 1999-11-23 |
| 5969425 | Borderless vias with CVD barrier layer | Robert Chen, John A. Iacoponi | 1999-10-19 |
| 5939766 | High quality capacitor for sub-micrometer integrated circuits | Andre Stolmeijer | 1999-08-17 |