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Gate structure and a transistor having asymmetric spacer elements and methods of forming the same |
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2008-04-08 |
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Three-dimensional integrated semiconductor devices |
— |
2005-09-13 |
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Richard C. Blish, II, Kurt Taylor |
2002-03-26 |
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Process to separate the doping of polygate and source drain regions in dual gate field effect transistors |
Scott Luning |
2001-11-20 |
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Borderless vias with CVD barrier layer |
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2000-12-12 |
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Method of controlling effective channel length of semiconductor device by non-doping implantation at elevated energies |
Jan Raebiger |
2000-08-01 |
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Method for obtaining a steep retrograde channel profile |
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1999-11-23 |
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Borderless vias with CVD barrier layer |
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1999-10-19 |
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High quality capacitor for sub-micrometer integrated circuits |
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1999-08-17 |