Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for avoiding lithographic rounding effects for semiconductor fabrication

Method for avoiding lithographic rounding effects for semiconductor fabrication

US Patent 5523258 · Granted Jun 4, 1996

Estimated economic value: $16,212,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Current source for read of programmable resistance memory cells2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Acceleration of data queries in memory2025
Adjustment of code rate as function of memory endurance state metric2025
Transistors with raised extension regions and semiconductor fins2025
Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensio2025
Quasi-volatile memory with reference bit line structure2025
Overwrite read methods for resistance switching memory devices2025
Status check using chip enable pin2024
Three-dimensional memory string array of thin-film ferroelectric transistors2024
Memory array reset read operation2024
Implementing variable number of bits per cell on storage devices2024