Issued Patents All Time
Showing 1–25 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11222679 | Packaged integrated circuit having a photodiode and a resistive memory | Nihaar N. Mahatme | 2022-01-11 |
| 10921390 | Magnetic attack detection in a magnetic random access memory (MRAM) | Nihaar N. Mahatme | 2021-02-16 |
| 10510616 | Post contact air gap formation | Douglas M. Reber | 2019-12-17 |
| 10262893 | Method of forming inter-level dielectric structures on semiconductor devices | Douglas M. Reber | 2019-04-16 |
| 10204860 | Semiconductor device with graphene encapsulated metal and method therefor | Douglas M. Reber | 2019-02-12 |
| 10103241 | Multigate transistor | Douglas M. Reber | 2018-10-16 |
| 10041993 | Safe operating area checking method and apparatus | Xavier Hours, Aldric L'Hernault, Christophe Oger | 2018-08-07 |
| 10038081 | Substrate contacts for a transistor | Douglas M. Reber | 2018-07-31 |
| 10014257 | Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures | Douglas M. Reber, Edward O. Travis | 2018-07-03 |
| 10008447 | Solar cell powered integrated circuit device and method therefor | Douglas M. Reber | 2018-06-26 |
| 9818642 | Method of forming inter-level dielectric structures on semiconductor devices | Douglas M. Reber | 2017-11-14 |
| 9716141 | Applications for nanopillar structures | Mark D. Hall | 2017-07-25 |
| 9712054 | Voltage and current limits for electronic device based on temperature range | Xavier Hours | 2017-07-18 |
| 9702925 | Semiconductor device with upset event detection and method of making | Mark D. Hall, Steven G. H. Anderson | 2017-07-11 |
| 9685405 | Fuse/resistor utilizing interconnect and vias and method of making | Douglas M. Reber, Edward O. Travis | 2017-06-20 |
| 9640430 | Semiconductor device with graphene encapsulated metal and method therefor | Douglas M. Reber | 2017-05-02 |
| 9515006 | 3D device packaging using through-substrate posts | Douglas M. Reber, Edward O. Travis | 2016-12-06 |
| 9508702 | 3D device packaging using through-substrate posts | Douglas M. Reber, Edward O. Travis | 2016-11-29 |
| 9508701 | 3D device packaging using through-substrate pillars | Douglas M. Reber, Edward O. Travis | 2016-11-29 |
| 9472418 | Method for forming a split-gate device | Mark D. Hall | 2016-10-18 |
| 9466569 | Though-substrate vias (TSVs) and method therefor | Douglas M. Reber | 2016-10-11 |
| 9455220 | Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures | Douglas M. Reber, Edward O. Travis | 2016-09-27 |
| 9443804 | Capping layer interface interruption for stress migration mitigation | Douglas M. Reber, Edward O. Travis | 2016-09-13 |
| 9443041 | Simulation system and method for testing a simulation of a device against one or more violation rules | Peter Abramowitz, Xavier Hours | 2016-09-13 |
| 9424379 | Simulation system and method for testing a simulation of a device against one or more violation rules | Xavier Hours, Pascal Caunegre, Christophe Oger | 2016-08-23 |