Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11694970 | Plated pillar dies having integrated electromagnetic shield layers | Rishi Bhooshan | 2023-07-04 |
| 10553508 | Semiconductor manufacturing using disposable test circuitry within scribe lanes | Sergio A. Ajuria, Phuc M. Nguyen | 2020-02-04 |
| 10522615 | Semiconductor package with embedded capacitor and methods of manufacturing same | Sergio A. Ajuria, Phuc M. Nguyen | 2019-12-31 |
| 10510616 | Post contact air gap formation | Mehul D. Shroff | 2019-12-17 |
| 10262893 | Method of forming inter-level dielectric structures on semiconductor devices | Mehul D. Shroff | 2019-04-16 |
| 10204860 | Semiconductor device with graphene encapsulated metal and method therefor | Mehul D. Shroff | 2019-02-12 |
| 10103241 | Multigate transistor | Mehul D. Shroff | 2018-10-16 |
| 10038081 | Substrate contacts for a transistor | Mehul D. Shroff | 2018-07-31 |
| 10014257 | Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures | Mehul D. Shroff, Edward O. Travis | 2018-07-03 |
| 10008447 | Solar cell powered integrated circuit device and method therefor | Mehul D. Shroff | 2018-06-26 |
| 9934349 | Method for verifying design rule checks | Inder Mohan Bhawnani, Ertugrul Demircan, Dwarka Prasad, Donald E. Smeltzer, Kenneth J. Danti | 2018-04-03 |
| 9818642 | Method of forming inter-level dielectric structures on semiconductor devices | Mehul D. Shroff | 2017-11-14 |
| 9685405 | Fuse/resistor utilizing interconnect and vias and method of making | Mehul D. Shroff, Edward O. Travis | 2017-06-20 |
| 9652577 | Integrated circuit design using pre-marked circuit element object library | Edward O. Travis, Ertugrul Demircan, Michael A. Stockinger | 2017-05-16 |
| 9640430 | Semiconductor device with graphene encapsulated metal and method therefor | Mehul D. Shroff | 2017-05-02 |
| 9601354 | Semiconductor manufacturing for forming bond pads and seal rings | Sergio A. Ajuria, Phuc M. Nguyen | 2017-03-21 |
| 9548266 | Semiconductor package with embedded capacitor and methods of manufacturing same | Sergio A. Ajuria, Phuc M. Nyugen | 2017-01-17 |
| 9515006 | 3D device packaging using through-substrate posts | Mehul D. Shroff, Edward O. Travis | 2016-12-06 |
| 9508702 | 3D device packaging using through-substrate posts | Mehul D. Shroff, Edward O. Travis | 2016-11-29 |
| 9508701 | 3D device packaging using through-substrate pillars | Mehul D. Shroff, Edward O. Travis | 2016-11-29 |
| 9466569 | Though-substrate vias (TSVs) and method therefor | Mehul D. Shroff | 2016-10-11 |
| 9455220 | Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures | Mehul D. Shroff, Edward O. Travis | 2016-09-27 |
| 9445050 | Teleconferencing environment having auditory and visual cues | Edward O. Travis | 2016-09-13 |
| 9443804 | Capping layer interface interruption for stress migration mitigation | Mehul D. Shroff, Edward O. Travis | 2016-09-13 |
| 9318409 | Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit | Mehul D. Shroff, Edward O. Travis | 2016-04-19 |