Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9245817 | Semiconductor device with embedded heat spreading | Edward O. Travis, Mehul D. Shroff | 2016-01-26 |
| 9236344 | Thin beam deposited fuse | Mehul D. Shroff, Edward O. Travis | 2016-01-12 |
| 9224692 | Semiconductor device having a nanotube layer and method for forming | — | 2015-12-29 |
| 9142507 | Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device | Mehul D. Shroff, Edward O. Travis | 2015-09-22 |
| 9134366 | Method for forming a packaged semiconductor device | Sergio A. Ajuria, Phuc M. Nguyen | 2015-09-15 |
| 9122812 | Semiconductor device with vias on a bridge connecting two buses | Mehul D. Shroff, Edward O. Travis | 2015-09-01 |
| 9122829 | Stress migration mitigation | Mehul D. Shroff, Edward O. Travis | 2015-09-01 |
| 9082824 | Method for forming an electrical connection between metal layers | Mehul D. Shroff, Edward O. Travis | 2015-07-14 |
| 9041209 | Method and apparatus to improve reliability of vias | Lawrence N. Herr | 2015-05-26 |
| 9032615 | Method for forming an electrical connection between metal layers | Edward O. Travis, Mehul D. Shroff | 2015-05-19 |
| 8987916 | Methods and apparatus to improve reliability of isolated vias | — | 2015-03-24 |
| 8972922 | Method for forming an electrical connection between metal layers | Mehul D. Shroff, Edward O. Travis | 2015-03-03 |
| 8946000 | Method for forming an integrated circuit having a programmable fuse | Mehul D. Shroff, Edward O. Travis | 2015-02-03 |
| 8941242 | Method of protecting against via failure and structure therefor | Mehul D. Shroff, Edward O. Travis | 2015-01-27 |
| 8883639 | Semiconductor device having a nanotube layer and method for forming | — | 2014-11-11 |
| 8832624 | Multi-layer process-induced damage tracking and remediation | Mehul D. Shroff, Edward O. Travis | 2014-09-09 |
| 8796841 | Semiconductor device with embedded heat spreading | Edward O. Travis, Mehul D. Shroff | 2014-08-05 |
| 8736071 | Semiconductor device with vias on a bridge connecting two buses | Mehul D. Shroff, Edward O. Travis | 2014-05-27 |
| 8707231 | Method and system for derived layer checking for semiconductor device design | Mehul D. Shroff, Edward O. Travis | 2014-04-22 |
| 8703507 | Method and apparatus to improve reliability of vias | — | 2014-04-22 |
| 8694926 | Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules | Mehul D. Shroff, Edward O. Travis | 2014-04-08 |
| 8640072 | Method for forming an electrical connection between metal layers | Mehul D. Shroff, Edward O. Travis | 2014-01-28 |
| 8601430 | Device matching tool and methods thereof | Mehul D. Shroff, Edward O. Travis | 2013-12-03 |
| 8595667 | Via placement and electronic circuit design processing method and electronic circuit design utilizing same | Mehul D. Shroff, Edward O. Travis | 2013-11-26 |
| 8581390 | Semiconductor device with heat dissipation | Edward O. Travis, Mehul D. Shroff | 2013-11-12 |