Issued Patents All Time
Showing 51–75 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8884241 | Incident capacitive sensor | Mark D. Hall | 2014-11-11 |
| 8877601 | Lateral capacitor and method of making | Mark D. Hall | 2014-11-04 |
| 8877568 | Methods of making logic transistors and non-volatile memory cells | Mark D. Hall | 2014-11-04 |
| 8872255 | Semiconductor devices with non-volatile memory cells | Mark D. Hall | 2014-10-28 |
| 8856705 | Mismatch verification device and methods thereof | Sanjay R. Parihar, Edward O. Travis | 2014-10-07 |
| 8832624 | Multi-layer process-induced damage tracking and remediation | Douglas M. Reber, Edward O. Travis | 2014-09-09 |
| 8796841 | Semiconductor device with embedded heat spreading | Edward O. Travis, Douglas M. Reber | 2014-08-05 |
| 8793632 | Techniques for electromigration stress determination in interconnects of an integrated circuit | Ertugrul Demircan | 2014-07-29 |
| 8756559 | Systems and methods for determining aging damage for semiconductor devices | Peter Abramowitz | 2014-06-17 |
| 8741719 | Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique | Mark D. Hall, Frank K. Baker, Jr. | 2014-06-03 |
| 8736071 | Semiconductor device with vias on a bridge connecting two buses | Douglas M. Reber, Edward O. Travis | 2014-05-27 |
| 8728886 | Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric | Mark D. Hall | 2014-05-20 |
| 8722493 | Logic transistor and non-volatile memory cell integration | Mark D. Hall | 2014-05-13 |
| 8716781 | Logic transistor and non-volatile memory cell integration | Mark D. Hall | 2014-05-06 |
| 8716089 | Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage | Mark D. Hall, Frank K. Baker, Jr. | 2014-05-06 |
| 8709883 | Implant for performance enhancement of selected transistors in an integrated circuit | William F. Johnstone, Chad Weintraub | 2014-04-29 |
| 8713498 | Method and system for physical verification using network segment current | Ertugrul Demircan | 2014-04-29 |
| 8707231 | Method and system for derived layer checking for semiconductor device design | Douglas M. Reber, Edward O. Travis | 2014-04-22 |
| 8694926 | Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules | Douglas M. Reber, Edward O. Travis | 2014-04-08 |
| 8669158 | Non-volatile memory (NVM) and logic integration | Mark D. Hall, Frank K. Baker, Jr. | 2014-03-11 |
| 8658497 | Non-volatile memory (NVM) and logic integration | Mark D. Hall | 2014-02-25 |
| 8640072 | Method for forming an electrical connection between metal layers | Douglas M. Reber, Edward O. Travis | 2014-01-28 |
| 8633080 | Methods of making multi-state non-volatile memory cells | Mark D. Hall | 2014-01-21 |
| 8624312 | Semiconductor device structure as a capacitor | Mark D. Hall | 2014-01-07 |
| 8601430 | Device matching tool and methods thereof | Douglas M. Reber, Edward O. Travis | 2013-12-03 |