Issued Patents All Time
Showing 76–100 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8595667 | Via placement and electronic circuit design processing method and electronic circuit design utilizing same | Douglas M. Reber, Edward O. Travis | 2013-11-26 |
| 8581390 | Semiconductor device with heat dissipation | Edward O. Travis, Douglas M. Reber | 2013-11-12 |
| 8574987 | Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric | Mark D. Hall | 2013-11-05 |
| 8569816 | Isolated capacitors within shallow trench isolation | Mark D. Hall | 2013-10-29 |
| 8564044 | Non-volatile memory and logic circuit process integration | Mark D. Hall | 2013-10-22 |
| 8557650 | Patterning a gate stack of a non-volatile memory (NVM) using a dummy gate stack | — | 2013-10-15 |
| 8536007 | Non-volatile memory cell and logic transistor integration | Mark D. Hall | 2013-09-17 |
| 8536006 | Logic and non-volatile memory (NVM) integration | Mark D. Hall | 2013-09-17 |
| 8524557 | Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic | Mark D. Hall, Frank K. Baker, Jr. | 2013-09-03 |
| 8510695 | Techniques for electromigration stress determination in interconnects of an integrated circuit | Ertugrul Demircan | 2013-08-13 |
| 8431471 | Method for integrating a non-volatile memory (NVM) | Jane A. Yater, Sung-Taeg Kang | 2013-04-30 |
| 8415217 | Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor | Bradley P. Smith | 2013-04-09 |
| 8399310 | Non-volatile memory and logic circuit process integration | Mark D. Hall | 2013-03-19 |
| 8389365 | Non-volatile memory and logic circuit process integration | Mark D. Hall | 2013-03-05 |
| 8343842 | Method for reducing plasma discharge damage during processing | David M. Schraub, Terry A. Breeden, James D. Legg, Ruiqi Tian | 2013-01-01 |
| 8318576 | Decoupling capacitors recessed in shallow trench isolation | Mark D. Hall | 2012-11-27 |
| 8318577 | Method of making a semiconductor device as a capacitor | Mark D. Hall | 2012-11-27 |
| 8202778 | Patterning a gate stack of a non-volatile memory (NVM) with simultaneous etch in non-NVM area | — | 2012-06-19 |
| 8021957 | Process of forming an electronic device including insulating layers having different strains | Paul A. Grudowski, Venkat R. Kolagunta | 2011-09-20 |
| 7951695 | Method for reducing plasma discharge damage during processing | David M. Schraub, Terry A. Breeden, James D. Legg, Ruiqi Tian | 2011-05-31 |
| 7858487 | Method and apparatus for indicating directionality in integrated circuit manufacturing | Edward O. Travis, Donald E. Smeltzer, Traci L. Smith | 2010-12-28 |
| 7843011 | Electronic device including insulating layers having different strains | Paul A. Grudowski, Venkat R. Kolagunta | 2010-11-30 |
| 7741221 | Method of forming a semiconductor device having dummy features | Ruiqi Tian, Willard E. Conley | 2010-06-22 |
| 7670760 | Treatment for reduction of line edge roughness | Jinmiao J. Shen, Jonathan Cobb, William D. Darlington, Brian Fisher, Mark D. Hall +2 more | 2010-03-02 |
| 7635920 | Method and apparatus for indicating directionality in integrated circuit manufacturing | Edward O. Travis, Donald E. Smeltzer, Traci L. Smith | 2009-12-22 |