Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8741743 | Integrated assist features for epitaxial growth | Omar Zia, Nigel G. Cave, Venkat R. Kolagunta, Edward O. Travis | 2014-06-03 |
| 8722519 | Integrated assist features for epitaxial growth | Omar Zia, Edward O. Travis | 2014-05-13 |
| 8343842 | Method for reducing plasma discharge damage during processing | David M. Schraub, Terry A. Breeden, James D. Legg, Mehul D. Shroff | 2013-01-01 |
| 8003539 | Integrated assist features for epitaxial growth | Omar Zia, Edward O. Travis | 2011-08-23 |
| 7951695 | Method for reducing plasma discharge damage during processing | David M. Schraub, Terry A. Breeden, James D. Legg, Mehul D. Shroff | 2011-05-31 |
| 7785983 | Semiconductor device having tiles for dual-trench integration and method therefor | Omar Zia | 2010-08-31 |
| 7741221 | Method of forming a semiconductor device having dummy features | Willard E. Conley, Mehul D. Shroff | 2010-06-22 |
| 7565639 | Integrated assist features for epitaxial growth bulk tiles with compensation | Omar Zia, Nigel G. Cave, Venkat R. Kolagunta, Edward O. Travis | 2009-07-21 |
| 7470624 | Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation | Omar Zia, Nigel G. Cave, Venkat R. Kolagunta, Edward O. Travis | 2008-12-30 |
| 7322014 | Method of implementing polishing uniformity and modifying layout data | Edward O. Travis, Nathan A. Aldrich | 2008-01-22 |
| 7276435 | Die level metal density gradient for improved flip chip package reliability | Scott K. Pozder, Kevin J. Hess, Edward O. Travis, Trent S. Uehling, Brett P. Wilkerson +1 more | 2007-10-02 |
| 7146593 | Method of implementing polishing uniformity and modifying layout data | Edward O. Travis, Nathan A. Aldrich | 2006-12-05 |
| 6905967 | Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems | Edward O. Travis, Thomas M. Brown | 2005-06-14 |
| 6611045 | Method of forming an integrated circuit device using dummy features and structure thereof | Edward O. Travis, Sejal Chheda | 2003-08-26 |
| 6593226 | Method for adding features to a design layout and process for designing a mask | Edward O. Travis, Aykut Dengi, Sejal Chheda, Tat-Kwan Yu, Mark S. Roberton +2 more | 2003-07-15 |
| 6489083 | Selective sizing of features to compensate for resist thickness variations in semiconductor devices | Bradley P. Smith, Edward O. Travis, Sejal Chheda | 2002-12-03 |
| 6459156 | Semiconductor device, a process for a semiconductor device, and a process for making a masking database | Edward O. Travis, Sejal Chheda, Bradley P. Smith | 2002-10-01 |
| 6396158 | Semiconductor device and a process for designing a mask | Edward O. Travis, Aykut Dengi, Sejal Chheda, Tat-Kwan Yu, Mark S. Roberton | 2002-05-28 |