Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6429795 | Method and apparatus for transforming pseudorandom binary patterns into test stimulus patterns appropriate for circuits having 1 of N encoded inputs | — | 2002-08-06 |
| 6412085 | Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state | Stephen C. Horne | 2002-06-25 |
| 6295622 | Method and apparatus for transforming pseudorandom binary test patterns into test stimulus patterns appropriate for circuits having 1 of N encoded inputs | — | 2001-09-25 |
| 6272653 | Method and apparatus for built-in self-test of logic circuitry | — | 2001-08-07 |