Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8397190 | Method for manipulating and repartitioning a hierarchical integrated circuit design | Robert D. Kenney, Raymond Cheung Yeung, Paul K. Miller, Jeffrey B. Reed | 2013-03-12 |
| 7219326 | Physical realization of dynamic logic using parameterized tile partitioning | Jeffrey B. Reed, James S. Blomgren, Timothy A. Olson, Thomas W. Rudwick, III | 2007-05-15 |
| 6732346 | Generation of route rules | Stephen C. Horne, Gopal Vijayan | 2004-05-04 |
| 6445213 | Method for calculating dynamic logic block propagation delay targets using time borrowing | Gopal Vijayan, James S. Blomgren, Stephen C. Horne | 2002-09-03 |