Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Paul K. Miller — 24 Patents

AMD: 18 patents #633 of 9,280Top 7%
IBM: 2 patents #32,909 of 70,183Top 50%
EGEurosil Electronic Gmbh: 1 patents #2 of 12Top 20%
TGThe Gsi Group: 1 patents #90 of 181Top 50%
Apple: 1 patents #12,397 of 18,612Top 70%
TITexas Instruments: 1 patents #7,388 of 12,488Top 60%
Vandalia, IL: #2 of 17 inventorsTop 15%
Illinois: #2,896 of 84,256 inventorsTop 4%
Overall (All Time): #168,038 of 4,157,543Top 5%
24 Patents All Time
Paul K. Miller has been granted 24 US patents while listed as an inventor at AMD. The first was granted in 1991 and the most recent in November 2016. Paul K. Miller ranks #168,038 of 4,157,543 US inventors in our database (top 4.0%). Patent records list Paul K. Miller in Vandalia, IL, US.

Patents per Year

Patents granted per year, 1991 to 2016Bar chart with a peak of 6 patents in 1999.peak 61991: 1 patents19911996: 2 patents19961998: 1 patents19981999: 6 patents19992000: 4 patents20002001: 3 patents20012002: 4 patents20022007: 1 patents20072013: 1 patents20132016: 1 patents2016

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9493957 Catwalk for a grain bin or the like and a plank used in the construction thereof Chirag Chandrakant Patel, Arron Justin Cochran, Robb Glenn Williams, Satheesh Kumar Somu 2016-11-15 $1,632,000
8397190 Method for manipulating and repartitioning a hierarchical integrated circuit design Robert D. Kenney, Raymond Cheung Yeung, Donald W. Glowka, Jeffrey B. Reed 2013-03-12 $106,410,000
7237065 Configurable cache system depending on instruction type Thang M. Tran, Raul A. Garibay, Jr., Muralidharan S. Chinnakonda 2007-06-26 $11,567,000
6460132 Massively parallel instruction predecoding 2002-10-01 $734,000
6405303 Massively parallel decoding and execution of variable-length instructions Gerald D. Zuraski, Jr. 2002-06-11 $2,353,000
6360317 Predecoding multiple instructions as one combined instruction and detecting branch to one of the instructions Rupaka Mahalingaiah 2002-03-19 $4,163,000
6339822 Using padded instructions in a block-oriented cache 2002-01-15 $19,594,000
6260134 Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte Gerald D. Zuraski, Jr., Syed Faisal Ahmed 2001-07-10 $4,638,000
6240506 Expanding instructions with variable-length operands to a fixed length 2001-05-29 $6,079,000
6192468 Apparatus and method for detecting microbranches early Rupaka Mahalingaiah 2001-02-20 $7,201,000
6167507 Apparatus and method for floating point exchange dispatch with reduced latency Rupaka Mahalingaiah 2000-12-26 $2,711,000
6161172 Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor Rammohan Narayan, Rupaka Mahalingaiah 2000-12-12 $4,351,000
6141740 Apparatus and method for microcode patching for generating a next address Rupaka Mahalingaiah 2000-10-31 $4,395,000
6081884 Embedding two different instruction sets within a single long instruction word using predecode bits 2000-06-27 $12,313,000
6009513 Apparatus and method for detecting microbranches early Rupaka Mahalingaiah 1999-12-28 $3,462,000
5978901 Floating point and multimedia unit with data type reclassification capability Mark Luedtke, Chris N. Hinds, Ashraf Ahmed 1999-11-02 $2,027,000
5933629 Apparatus and method for detecting microbranches early Rupaka Mahalingaiah 1999-08-03 $2,588,000
5913047 Pairing floating point exchange instruction with another floating point instruction to reduce dispatch latency Rupaka Mahalingaiah 1999-06-15 $3,878,000
5884058 Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor Rammohan Narayan, Rupaka Mahalingaiah 1999-03-16 $3,122,000
5867680 Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions Rammohan Narayan, Rupaka Mahalingaiah 1999-02-02 $5,243,000
5845102 Determining microcode entry points and prefix bytes using a parallel logic technique Rupaka Mahalingaiah 1998-12-01 $5,030,000
5548544 Method and apparatus for rounding the result of an arithmetic operation David Terrence Matheny, Michael P. Taborn 1996-08-20 $9,974,000
5491653 Differential carry-save adder and multiplier Michael P. Taborn 1996-02-13 $8,744,000
5029063 MOSFET multiplying circuit Ernst Lingstaedt 1991-07-02