Issued Patents All Time
Showing 25 most recent of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10212254 | Method and apparatus for enabling mobile cluster computing | — | 2019-02-19 |
| 9467494 | Method and apparatus for enabling mobile cluster computing | — | 2016-10-11 |
| 8769331 | Method and apparatus for securing digital devices while reducing power consumption | — | 2014-07-01 |
| 8683572 | Method and apparatus for providing continuous user verification in a packet-based network | — | 2014-03-25 |
| 8458453 | Method and apparatus for securing communication over public network | — | 2013-06-04 |
| 7970929 | Apparatus, system, and method for routing data to and from a host that is moved from one location on a communication system to another location on the communication system | — | 2011-06-28 |
| 7778259 | Network packet transmission mechanism | — | 2010-08-17 |
| 6912196 | Communication network and protocol which can efficiently maintain transmission across a disrupted network | — | 2005-06-28 |
| 6804235 | Address mapping mechanism enabling multi-domain addressing in communication networks | — | 2004-10-12 |
| 6788701 | Communication network having modular switches that enhance data throughput | Viren Kapadia | 2004-09-07 |
| 6754214 | Communication network having packetized security codes and a system for detecting security breach locations within the network | — | 2004-06-22 |
| 6654346 | Communication network across which packets of data are transmitted according to a priority scheme | Viren Kapadia | 2003-11-25 |
| 6643286 | Modular switches interconnected across a communication network to achieve minimal address mapping or translation between termination devices | Viren Kapadia | 2003-11-04 |
| 6587462 | Address mapping mechanism enabling multi-domain addressing in communication networks | — | 2003-07-01 |
| 6460116 | Using separate caches for variable and generated fixed-length instructions | — | 2002-10-01 |
| 6389512 | Microprocessor configured to detect updates to instructions outstanding within an instruction processing pipeline and computer system including same | Gerald D. Zuraski, Jr. | 2002-05-14 |
| 6360317 | Predecoding multiple instructions as one combined instruction and detecting branch to one of the instructions | Paul K. Miller | 2002-03-19 |
| 6269436 | Superscalar microprocessor configured to predict return addresses from a return stack storage | Thang M. Tran | 2001-07-31 |
| 6253309 | Forcing regularity into a CISC instruction set by padding instructions | — | 2001-06-26 |
| 6212621 | Method and system using tagged instructions to allow out-of-program-order instruction decoding | — | 2001-04-03 |
| 6192468 | Apparatus and method for detecting microbranches early | Paul K. Miller | 2001-02-20 |
| 6167507 | Apparatus and method for floating point exchange dispatch with reduced latency | Paul K. Miller | 2000-12-26 |
| 6161172 | Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor | Rammohan Narayan, Paul K. Miller | 2000-12-12 |
| 6141740 | Apparatus and method for microcode patching for generating a next address | Paul K. Miller | 2000-10-31 |
| 6134670 | Method and apparatus for generation and synchronization of distributed pulse clocked mechanism digital designs | — | 2000-10-17 |