Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6106573 | Apparatus and method for tracing microprocessor instructions | James K. Pickett | 2000-08-22 |
| 6092182 | Using ECC/parity bits to store predecode information | — | 2000-07-18 |
| 6085302 | Microprocessor having address generation units for efficient generation of memory operation addresses | Thang M. Tran | 2000-07-04 |
| 6073217 | Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor | Gerald D. Zuraski, Jr. | 2000-06-06 |
| 6065103 | Speculative store buffer | Thang M. Tran | 2000-05-16 |
| 6065126 | Method and apparatus for executing plurality of operations per clock cycle in a single processing unit with a self-timed and self-enabled distributed clock | Thang M. Tran | 2000-05-16 |
| 6016545 | Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor | Andrew McBride, Thang M. Tran | 2000-01-18 |
| 6014741 | Apparatus and method for predicting an end of a microcode loop | — | 2000-01-11 |
| 6014734 | Superscalar microprocessor configured to predict return addresses from a return stack storage | Thang M. Tran | 2000-01-11 |
| 6009513 | Apparatus and method for detecting microbranches early | Paul K. Miller | 1999-12-28 |
| 5987592 | Flexible resource access in a microprocessor | — | 1999-11-16 |
| 5983337 | Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction | Thang M. Tran | 1999-11-09 |
| 5961580 | Apparatus and method for efficiently calculating a linear address in a microprocessor | — | 1999-10-05 |
| 5960467 | Apparatus for efficiently providing memory operands for instructions | Thang M. Tran | 1999-09-28 |
| 5933629 | Apparatus and method for detecting microbranches early | Paul K. Miller | 1999-08-03 |
| 5933618 | Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction | Thang M. Tran, James K. Pickett | 1999-08-03 |
| 5933626 | Apparatus and method for tracing microprocessor instructions | James K. Pickett | 1999-08-03 |
| 5926646 | Context-dependent memory-mapped registers for transparent expansion of a register file | James K. Pickett, Brian D. McMinn | 1999-07-20 |
| 5913047 | Pairing floating point exchange instruction with another floating point instruction to reduce dispatch latency | Paul K. Miller | 1999-06-15 |
| 5898865 | Apparatus and method for predicting an end of loop for string instructions | — | 1999-04-27 |
| 5892936 | Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register | Thang M. Tran, James K. Pickett | 1999-04-06 |
| 5884058 | Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor | Rammohan Narayan, Paul K. Miller | 1999-03-16 |
| 5881278 | Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch | Thang M. Tran | 1999-03-09 |
| 5870578 | Workload balancing in a microprocessor for reduced instruction dispatch stalling | Thomas S. Green | 1999-02-09 |
| 5867680 | Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions | Rammohan Narayan, Paul K. Miller | 1999-02-02 |