Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9651617 | Full address coverage during memory array built-in self test with minimum transitions | Edward Bryann C. Fernandez, Thomas Jew | 2017-05-16 |
| 9396780 | Decoder | Padmaraj Sanjeevarao | 2016-07-19 |
| 9191007 | Latching level shifter and method of operation | Jon S. Choy | 2015-11-17 |
| 8913436 | Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage | Padmaraj Sanjeevarao | 2014-12-16 |
| 8625365 | Memory device and method using encode values for access error condition detection | Padmaraj Sanjeevarao | 2014-01-07 |
| 8151075 | Multiple access type memory and method of operation | Timothy J. Strauss, William C. Moyer | 2012-04-03 |
| 7733126 | Negative voltage generation | Jon S. Choy, Padmaraj Sanjeevarao | 2010-06-08 |
| 7701785 | Memory with high speed sensing | Padmaraj Sanjeevarao, Tahmina Akhter | 2010-04-20 |
| 7692989 | Non-volatile memory having a static verify-read output data path | Padmaraj Sanjeevarao | 2010-04-06 |
| 7564716 | Memory device with retained indicator of read reference level | Ronald J. Syzdek, Xiaojie He | 2009-07-21 |
| 7542351 | Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor | Jon S. Choy | 2009-06-02 |
| 7446566 | Level shifter | — | 2008-11-04 |
| 7428172 | Concurrent programming and program verification of floating gate transistor | Jon S. Choy, Thomas Jew | 2008-09-23 |
| 6745357 | Dynamic logic scan gate method and apparatus | Stephen C. Horne, James S. Blomgren, Michael R. Seningen | 2004-06-01 |
| 6226200 | In-circuit memory array bit cell threshold voltage distribution measurement | Richard K. Eguchi, Thomas Jew | 2001-05-01 |
| 5991201 | Non-volatile memory with over-program protection and method therefor | Clinton C. K. Kuo, Thomas Jew | 1999-11-23 |
| 5365121 | Charge pump with controlled ramp rate | Bruce L. Morton | 1994-11-15 |