Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11742012 | Memory read circuitry with a flipped voltage follower | Karthik Ramanan, Jon S. Choy | 2023-08-29 |
| 11521692 | Memory with one-time programmable (OTP) cells and reading operations thereof | Jon S. Choy, Jacob T. Williams, Karthik Ramanan, Maurits Mario Nicolaas Storms | 2022-12-06 |
| 11328784 | Memory with cells having multiple select transistors | Jon S. Choy | 2022-05-10 |
| 11289144 | Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation | Jon S. Choy, Karthik Ramanan, Jacob T. Williams | 2022-03-29 |
| 11250898 | Non-volatile memory with multiplexer transistor regulator circuit | Jacob T. Williams, Karthik Ramanan, Jon S. Choy | 2022-02-15 |
| 11170849 | Memory with select line voltage control | Jon S. Choy, Jacob T. Williams | 2021-11-09 |
| 11049539 | Magnetoresistive random access memory (MRAM) with OTP cells | Jon S. Choy, Anirban Roy | 2021-06-29 |
| 10573364 | Magnetic disturb diagnostic system for MRAM | Richard K. Eguchi, Anirban Roy | 2020-02-25 |
| 9396780 | Decoder | David W. Chrudimsky | 2016-07-19 |
| 8913436 | Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage | David W. Chrudimsky | 2014-12-16 |
| 8737137 | Flash memory with bias voltage for word line/row driver | Jon S. Choy | 2014-05-27 |
| 8625365 | Memory device and method using encode values for access error condition detection | David W. Chrudimsky | 2014-01-07 |
| 7733126 | Negative voltage generation | Jon S. Choy, David W. Chrudimsky | 2010-06-08 |
| 7701785 | Memory with high speed sensing | Tahmina Akhter, David W. Chrudimsky | 2010-04-20 |
| 7692989 | Non-volatile memory having a static verify-read output data path | David W. Chrudimsky | 2010-04-06 |
| 7055118 | Scan chain verification using symbolic simulation | Harinath B. Kamepalli, Chang Jin PARK | 2006-05-30 |