Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9176799 | Hop-by-hop error detection in a server system | Min Xu, Sean Lie | 2015-11-03 |
| 8086825 | Processing pipeline having stage-specific thread selection and method thereof | Sean Lie, Marius Evers | 2011-12-27 |
| 7861066 | Mechanism for predicting and suppressing instruction replay in a processor | Ashutosh Dhodapkar, Michael G. Butler | 2010-12-28 |
| 7818542 | Method and apparatus for length decoding variable length instructions | Sean Lie | 2010-10-19 |
| 7818543 | Method and apparatus for length decoding and identifying boundaries of variable length instructions | Sean Lie | 2010-10-19 |
| 7793080 | Processing pipeline having parallel dispatch and method thereof | Sean Lie | 2010-09-07 |
| 7743232 | Multiple-core processor with hierarchical microcode store | Bruce R. Holloway, Sean Lie, Michael G. Butler | 2010-06-22 |
| 7725690 | Distributed dispatch with concurrent, out-of-order dispatch | Sean Lie | 2010-05-25 |
| 7685410 | Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects | Sean Lie | 2010-03-23 |
| 7117290 | MicroTLB and micro tag for reducing power in a processor | S. Craig Nelson | 2006-10-03 |
| 7051300 | Method and system for architectural power estimation | Stephan G. Meier, Leslie Barnes, Paul Keltcher | 2006-05-23 |
| 6553477 | Microprocessor and address translation method for microprocessor | Murali V. Krishna, Vipul Parikh, Michael G. Butler, Masahito Kubo | 2003-04-22 |
| 5966530 | Structure and method for instruction boundary machine state restoration | John Szeto, Niteen A. Patkar, Michael C. Shebanow | 1999-10-12 |
| 5896526 | Programmable instruction trap system and method | Sunil W. Savkar, Farnad Sajjadian, Michael C. Shebanow | 1999-04-20 |
| 5838940 | Method and apparatus for rotating active instructions in a parallel data processor | Sunil W. Savkar, Michael C. Shebanow, Farnad Sajjadian | 1998-11-17 |
| 5790443 | Mixed-modulo address generation using shadow segment registers | Shalesh Thusoo, James S. Blomgren, Betty Y. Kikuta | 1998-08-04 |
| 5790826 | Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes | Shalesh Thusoo, James S. Blomgren | 1998-08-04 |
| 5751985 | Processor structure and method for tracking instruction status to maintain precise state | John Szeto, Niteen A. Patkar, Michael C. Shebanow | 1998-05-12 |
| 5687336 | Stack push/pop tracking and pairing in a pipelined processor | Shalesh Thusoo, James S. Blomgren | 1997-11-11 |
| 5675759 | Method and apparatus for register management using issue sequence prior physical register and register association validity information | Michael C. Shebanow, Ravi Swami, Niteen A. Patkar | 1997-10-07 |
| 5673426 | Processor structure and method for tracking floating-point exceptions | John Szeto, Michael C. Shebanow | 1997-09-30 |
| 5659721 | Processor structure and method for checkpointing instructions to maintain precise state | John Szeto, Niteen A. Patkar, Michael C. Shebanow | 1997-08-19 |
| 5655115 | Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation | Michael C. Shebanow, Hideki Osone, Takumi Maruyama | 1997-08-05 |
| 5651124 | Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state | John Szeto, Niteen A. Patkar, Michael C. Shebanow, Michael A. Simone | 1997-07-22 |
| 5649136 | Processor structure and method for maintaining and restoring precise state at any instruction boundary | John Szeto, Niteen A. Patkar, Michael C. Shebanow | 1997-07-15 |