Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5784586 | Addressing method for executing load instructions out of order with respect to store instructions | Michael C. Shebanow | 1998-07-21 |
| 5745726 | Method and apparatus for selecting the oldest queued instructions without data dependencies | Michael C. Shebanow, John Gmuender, John Szeto, Takumi Maruyama, DeForest Tovey | 1998-04-28 |
| 5651124 | Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state | Gene W. Shen, John Szeto, Niteen A. Patkar, Michael C. Shebanow | 1997-07-22 |
| 5638312 | Method and apparatus for generating a zero bit status flag in a microprocessor | — | 1997-06-10 |