| 7263642 |
Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system |
Samy R. Makar |
2007-08-28 |
| 7013456 |
Profiling execution of computer programs |
Korbin S. Van Dyke, Paul H. Hohensee, David L. Reese, John S. Yates, Jr., T. R. Ramesh +3 more |
2006-03-14 |
| 6941545 |
Profiling of computer programs executing in virtual memory systems |
David L. Reese, John S. Yates, Jr., Paul H. Hohensee, Korbin S. Van Dyke, T. R. Ramesh +2 more |
2005-09-06 |
| 6826748 |
Profiling program execution into registers of a computer |
Paul H. Hohensee, David L. Reese, John S. Yates, Jr., Korbin S. Van Dyke, T. R. Ramesh +2 more |
2004-11-30 |
| 6775756 |
Method and apparatus for out of order memory processing within an in order processor |
Shalesh Thusoo, Jim Lin |
2004-08-10 |
| 6745318 |
Method and apparatus of configurable processing |
Sanjay Mansingh, Korbin S. Van Dyke, Stephen C. Hale, Dee Tovey, Nital Patwa +1 more |
2004-06-01 |
| 6701426 |
Switching between a plurality of branch prediction processes based on which instruction set is operational wherein branch history data structures are the same for the plurality of instruction sets |
Greg L. Ries, Ronak Subhas Patel, Korbin S. Van Dyke, T. R. Ramesh |
2004-03-02 |
| 6643726 |
Method of manufacture and apparatus of an integrated computing system |
Ali Alasti, Don A. Van Dyke, Korbin S. Van Dyke, Shalesh Thusoo, Stephen C. Purcell +1 more |
2003-11-04 |
| 6578134 |
Multi-branch resolution |
Korbin S. Van Dyke, Shalesh Thusoo, TR Ramesh |
2003-06-10 |
| 6449671 |
Method and apparatus for busing data elements |
Stephen C. Purcell, Shalesh Thusoo, Korbin S. Van Dyke |
2002-09-10 |
| 6430646 |
Method and apparatus for interfacing a processor with a bus |
Shalesh Thusoo, Korbin S. Van Dyke, Stephen C. Purcell |
2002-08-06 |
| 6389519 |
Method and apparatus for providing probe based bus locking and address locking |
Shalesh Thusoo |
2002-05-14 |
| 5966530 |
Structure and method for instruction boundary machine state restoration |
Gene W. Shen, John Szeto, Michael C. Shebanow |
1999-10-12 |
| 5751985 |
Processor structure and method for tracking instruction status to maintain precise state |
Gene W. Shen, John Szeto, Michael C. Shebanow |
1998-05-12 |
| 5708788 |
Method for adjusting fetch program counter in response to the number of instructions fetched and issued |
Akira Katsuno, Sunil W. Savkar, Michael C. Shebanow |
1998-01-13 |
| 5675759 |
Method and apparatus for register management using issue sequence prior physical register and register association validity information |
Michael C. Shebanow, Gene W. Shen, Ravi Swami |
1997-10-07 |
| 5659721 |
Processor structure and method for checkpointing instructions to maintain precise state |
Gene W. Shen, John Szeto, Michael C. Shebanow |
1997-08-19 |
| 5651124 |
Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state |
Gene W. Shen, John Szeto, Michael C. Shebanow, Michael A. Simone |
1997-07-22 |
| 5649136 |
Processor structure and method for maintaining and restoring precise state at any instruction boundary |
Gene W. Shen, John Szeto, Michael C. Shebanow |
1997-07-15 |
| 5644742 |
Processor structure and method for a time-out checkpoint |
Gene W. Shen, John Szeto, Michael C. Shebanow |
1997-07-01 |
| 5632028 |
Hardware support for fast software emulation of unimplemented instructions |
Shalesh Thusoo, Farnad Sajjadian, Jaspal Kohli |
1997-05-20 |
