Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10885202 | Method and apparatus to provide secure application execution | Francis X. McKeen, Carlos V. Rozas, Uday Savagaonkar, Simon P. Johnson, Vincent R. Scarlata +16 more | 2021-01-05 |
| 10102380 | Method and apparatus to provide secure application execution | Francis X. McKeen, Carlos V. Rozas, Uday Savagaonkar, Simon P. Johnson, Vincent R. Scarlata +16 more | 2018-10-16 |
| 9087200 | Method and apparatus to provide secure application execution | Francis X. McKeen, Carlos V. Rozas, Uday Savagaonkar, Simon P. Johnson, Vincent R. Scarlata +16 more | 2015-07-21 |
| 8677163 | Context state management for processor feature sets | Michael Mishaeli, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh R. Sha +7 more | 2014-03-18 |
| 8635415 | Managing and implementing metadata in central processing unit using register extensions | Baiju V. Patel, Rajeev Gopalakrishna, Andrew F. Glew, Robert J. Kushlis, Joseph F. Cihula +7 more | 2014-01-21 |
| 8631261 | Context state management for processor feature sets | Michael Mishaeli, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh Shah +7 more | 2014-01-14 |
| 8381223 | Method and apparatus for dynamic allocation of processing resources | Korbin S. Van Dyke, Paul Campbell, Ali Alasti, Stephen C. Purcell | 2013-02-19 |
| 7987465 | Method and apparatus for dynamic allocation of processing resources | Korbin S. Van Dyke, Paul Campbell, Ali Alasti, Stephen C. Purcell | 2011-07-26 |
| 7661107 | Method and apparatus for dynamic allocation of processing resources | Korbin S. Van Dyke, Paul Campbell, Ali Alasti, Stephen C. Purcell | 2010-02-09 |
| 7254231 | Encryption/decryption instruction set enhancement | Korbin S. Van Dyke, Stephen C. Purcell | 2007-08-07 |
| 7047394 | Computer for execution of RISC and CISC instruction sets | Korbin S. Van Dyke, Paul Campbell | 2006-05-16 |
| 6904515 | Multi-instruction set flag preservation apparatus and method | — | 2005-06-07 |
| 6643726 | Method of manufacture and apparatus of an integrated computing system | Niteen A. Patkar, Ali Alasti, Korbin S. Van Dyke, Shalesh Thusoo, Stephen C. Purcell +1 more | 2003-11-04 |
| 6195676 | Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes | George A. Spix, Diane M. Wengelski, Stuart Hawkinson, Mark D. Johnson, Jeremiah D. Burke +16 more | 2001-02-27 |
| 5745721 | Partitioned addressing apparatus for vector/scalar registers | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1998-04-28 |
| 5717881 | Data processing system for processing one and two parcel instructions | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1998-02-10 |
| 5706490 | Method of processing conditional branch instructions in scalar/vector processor | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1998-01-06 |
| 5659706 | Vector/scalar processor with simultaneous processing and instruction cache filling | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1997-08-19 |
| 5640524 | Method and apparatus for chaining vector instructions | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1997-06-17 |
| 5623650 | Method of processing a sequence of conditional vector IF statements | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1997-04-22 |
| 5598547 | Vector processor having functional unit paths of differing pipeline lengths | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1997-01-28 |
| 5544337 | Vector processor having registers for control by vector resisters | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1996-08-06 |
| 5430884 | Scalar/vector processor | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman +3 more | 1995-07-04 |
| 5307478 | Method for inserting a path instruction during compliation of computer programs for processors having multiple functional units | James C. Rasbold | 1994-04-26 |
| 5202975 | Method for optimizing instruction scheduling for a processor having multiple functional resources | James C. Rasbold | 1993-04-13 |