Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11360780 | Instruction-level context switch in SIMD processor | Benjiman L. Goodman, Terence M. Potter, Anjana Rajendran, Jeffrey T. Brady, Brian K. Reynolds | 2022-06-14 |
| 11204774 | Thread-group-scoped gate instruction | Benjiman L. Goodman, Anjana Rajendran, Terence M. Potter | 2021-12-21 |
| 7113969 | Formatting denormal numbers for processing in a pipelined floating point unit | Daniel W. Green, Atul Dhablania | 2006-09-26 |
| 6907518 | Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same | Nicholas Samra, Ram Gummadi | 2005-06-14 |
| 6801924 | Formatting denormal numbers for processing in a pipelined floating point unit | Daniel W. Green, Atul Dhablania | 2004-10-05 |
| 6757812 | Leading bit prediction with in-parallel correction | Daniel W. Green, Atul Dhablania, Bang-Thu Nguyen | 2004-06-29 |
| 6714957 | System and method for efficient processing of denormal results as hardware exceptions | — | 2004-03-30 |
| 6629231 | System and method for efficient register file conversion of denormal numbers between scalar and SIMD formats | — | 2003-09-30 |
| 6581155 | Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same | Nicholas Samra, Ram Gummadi | 2003-06-17 |
| 6523050 | Integer to floating point conversion using one's complement with subsequent correction to eliminate two's complement in critical path | Atul Dhablania | 2003-02-18 |
| 6405232 | Leading bit prediction with in-parallel correction | Daniel W. Green, Atul Dhablania, Bang-Thu Nguyen | 2002-06-11 |
| 5745721 | Partitioned addressing apparatus for vector/scalar registers | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1998-04-28 |
| 5717881 | Data processing system for processing one and two parcel instructions | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1998-02-10 |
| 5706490 | Method of processing conditional branch instructions in scalar/vector processor | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1998-01-06 |
| 5659706 | Vector/scalar processor with simultaneous processing and instruction cache filling | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1997-08-19 |
| 5640524 | Method and apparatus for chaining vector instructions | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1997-06-17 |
| 5623650 | Method of processing a sequence of conditional vector IF statements | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1997-04-22 |
| 5598547 | Vector processor having functional unit paths of differing pipeline lengths | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1997-01-28 |
| 5544337 | Vector processor having registers for control by vector resisters | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1996-08-06 |
| 5430884 | Scalar/vector processor | Douglas R. Beard, Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Alexander A. Silbey +3 more | 1995-07-04 |