Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12376062 | Detecting profile-based wireless mesh node failover in communication networks | Zhuangzhi Duo | 2025-07-29 |
| 12279115 | Instant secure wireless network setup | Zhuangzhi Duo | 2025-04-15 |
| 12075246 | Securing transmission paths in a mesh network | Zhuangzhi Duo | 2024-08-27 |
| 12069480 | Elastic security services load balancing in a wireless mesh network | Zhuangzhi Duo | 2024-08-20 |
| 12056237 | Analysis of historical network traffic to identify network vulnerabilities | Zhuangzhi Duo | 2024-08-06 |
| 12058147 | Visualization tool for real-time network risk assessment | F. William Conner, MinhDung Joe NguyenLe, Richard Chio, Justin Jose, Lalith Kumar Dampanaboina | 2024-08-06 |
| 12022295 | Streamlined creation and expansion of a wireless mesh network | Zhuangzhi Duo | 2024-06-25 |
| 11997635 | Establishing simultaneous mesh node connections | Zhuangzhi Duo | 2024-05-28 |
| 11729621 | Elastic security services and load balancing in a wireless mesh network | Zhuangzhi Duo | 2023-08-15 |
| 11693961 | Analysis of historical network traffic to identify network vulnerabilities | Zhuangzhi Duo | 2023-07-04 |
| 11638149 | Instant secure wireless network setup | Zhuangzhi Duo | 2023-04-25 |
| 11388176 | Visualization tool for real-time network risk assessment | F. William Conner, MinhDung Joe NguyenLe, Richard Chio, Justin Jose, Lalith Kumar Dampanaboina | 2022-07-12 |
| 11310665 | Elastic security services and load balancing in a wireless mesh network | Zhuangzhi Duo | 2022-04-19 |
| 10972916 | Instant secure wireless network setup | Zhuangzhi Duo | 2021-04-06 |
| 10902122 | Just in time memory analysis for malware detection | Soumyadipta Das, Aleksandr Dubrovsky, Igor Korsunsky, John Gmuender | 2021-01-26 |
| 7113969 | Formatting denormal numbers for processing in a pipelined floating point unit | Daniel W. Green, Jeffrey A. Lohman | 2006-09-26 |
| 6965906 | Converting negative floating point numbers to integer notation without two's complement hardware | — | 2005-11-15 |
| 6954912 | Error detection in dynamic logic circuits | Pranjal Srivastava, Ajay Naini | 2005-10-11 |
| 6801924 | Formatting denormal numbers for processing in a pipelined floating point unit | Daniel W. Green, Jeffrey A. Lohman | 2004-10-05 |
| 6757812 | Leading bit prediction with in-parallel correction | Daniel W. Green, Jeffrey A. Lohman, Bang-Thu Nguyen | 2004-06-29 |
| 6721772 | Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls | Daniel W. Green | 2004-04-13 |
| 6654774 | Generation of sign extended shifted numerical values | Takumi Maruyama, Robert S. Grondalski | 2003-11-25 |
| 6523050 | Integer to floating point conversion using one's complement with subsequent correction to eliminate two's complement in critical path | Jeffrey A. Lohman | 2003-02-18 |
| 6490606 | Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls | Daniel W. Green | 2002-12-03 |
| 6415308 | Converting negative floating point numbers to integer notation without two's complement hardware | — | 2002-07-02 |