Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7328371 | Core redundancy in a chip multiprocessor for highly reliable systems | Vydhyanathan Kalyanasundharam, William A. Hughes, Philip E. Madrid, Scott White | 2008-02-05 |
| 6954912 | Error detection in dynamic logic circuits | Pranjal Srivastava, Atul Dhablania | 2005-10-11 |
| 6603333 | Method and apparatus for reduction of noise sensitivity in dynamic logic circuits | James Vinh, Pranjal Srivastava, Robert S. Grondalski | 2003-08-05 |
| 6542423 | Read port design and method for register array | Vydhyanathan Kalyanasundharam | 2003-04-01 |
| 6209083 | Processor having selectable exception handling modes | Robert Maher | 2001-03-27 |
| 5523961 | Converting biased exponents from single/double precision to extended precision without requiring an adder | — | 1996-06-04 |
| 5276635 | Method and apparatus for performing carry look-ahead addition in a data processor | William C. Anderson | 1994-01-04 |
| 5265043 | Wallace tree multiplier array having an improved layout topology | William C. Anderson, Lisa J. Craft | 1993-11-23 |
| 5220525 | Recoded iterative multiplier | William C. Anderson | 1993-06-15 |