Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12219057 | Implementing trusted executing environments across multiple processor devices | Philip J. Rogers, Mark A. Overby, Vyas Venkataraman, Naveen Cherukuri, Gobikrishna Dhanuskodi +4 more | 2025-02-04 |
| 12141268 | Secure execution for multiple processor devices using trusted executing environments | Philip J. Rogers, Mark A. Overby, Vyas Venkataraman, Naveen Cherukuri, Gobikrishna Dhanuskodi +4 more | 2024-11-12 |
| 10452566 | Storing secure state information in translation lookaside buffer cache lines | Steven E. Molnar, James Leroy Deming | 2019-10-22 |
| 9946658 | Memory interface design having controllable internal and external interfaces for bypassing defective memory | J. Arjun Prabhu | 2018-04-17 |
| 7685371 | Hierarchical flush barrier mechanism with deadlock avoidance | Samuel H. Duncan, Robert A. Alfieri, John H. Edmondson, David W. Nuechterlein | 2010-03-23 |
| 7631152 | Determining memory flush states for selective heterogeneous memory flushes | Robert A. Alfieri | 2009-12-08 |
| 5745721 | Partitioned addressing apparatus for vector/scalar registers | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1998-04-28 |
| 5717881 | Data processing system for processing one and two parcel instructions | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1998-02-10 |
| 5706490 | Method of processing conditional branch instructions in scalar/vector processor | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1998-01-06 |
| 5659706 | Vector/scalar processor with simultaneous processing and instruction cache filling | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-08-19 |
| 5640524 | Method and apparatus for chaining vector instructions | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-06-17 |
| 5623650 | Method of processing a sequence of conditional vector IF statements | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-04-22 |
| 5598547 | Vector processor having functional unit paths of differing pipeline lengths | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-01-28 |
| 5544337 | Vector processor having registers for control by vector resisters | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1996-08-06 |
| 5430884 | Scalar/vector processor | Douglas R. Beard, Andrew Everett Phelps, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1995-07-04 |