| 8065504 |
Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor |
John S. Yates, Jr., David L. Reese, Paul H. Hohensee, Korbin S. Van Dyke, Tiruvur R. Ramesh |
2011-11-22 |
| 7240255 |
Area efficient BIST system for memories |
Charles Akum Njinda, Hao Wang |
2007-07-03 |
| 7228404 |
Managing instruction side-effects |
Ronak Subhas Patel, Korbin S. Van Dyke, T. R. Ramesh, Gurjeet S. Saund, Sanjay Mansingh +1 more |
2007-06-05 |
| 7013456 |
Profiling execution of computer programs |
Korbin S. Van Dyke, Paul H. Hohensee, David L. Reese, John S. Yates, Jr., T. R. Ramesh +3 more |
2006-03-14 |
| 6941545 |
Profiling of computer programs executing in virtual memory systems |
David L. Reese, John S. Yates, Jr., Paul H. Hohensee, Korbin S. Van Dyke, T. R. Ramesh +2 more |
2005-09-06 |
| 6934832 |
Exception mechanism for a computer |
Korbin S. Van Dyke, Paul Campbell, T. R. Ramesh, Alan McNaughton |
2005-08-23 |
| 6826748 |
Profiling program execution into registers of a computer |
Paul H. Hohensee, David L. Reese, John S. Yates, Jr., Korbin S. Van Dyke, T. R. Ramesh +2 more |
2004-11-30 |
| 6775756 |
Method and apparatus for out of order memory processing within an in order processor |
Niteen A. Patkar, Jim Lin |
2004-08-10 |
| 6643726 |
Method of manufacture and apparatus of an integrated computing system |
Niteen A. Patkar, Ali Alasti, Don A. Van Dyke, Korbin S. Van Dyke, Stephen C. Purcell +1 more |
2003-11-04 |
| 6578134 |
Multi-branch resolution |
Korbin S. Van Dyke, Niteen A. Patkar, TR Ramesh |
2003-06-10 |
| 6449671 |
Method and apparatus for busing data elements |
Niteen A. Patkar, Stephen C. Purcell, Korbin S. Van Dyke |
2002-09-10 |
| 6430646 |
Method and apparatus for interfacing a processor with a bus |
Niteen A. Patkar, Korbin S. Van Dyke, Stephen C. Purcell |
2002-08-06 |
| 6389519 |
Method and apparatus for providing probe based bus locking and address locking |
Niteen A. Patkar |
2002-05-14 |
| 5848264 |
Debug and video queue for multi-processor chip |
Brian R. Baird, David E. Richter, David Matthew James Stark, James S. Blomgren |
1998-12-08 |
| 5822602 |
Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity |
— |
1998-10-13 |
| 5809272 |
Early instruction-length pre-decode of variable-length instructions in a superscalar processor |
James S. Blomgren |
1998-09-15 |
| 5790443 |
Mixed-modulo address generation using shadow segment registers |
Gene W. Shen, James S. Blomgren, Betty Y. Kikuta |
1998-08-04 |
| 5790826 |
Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes |
Gene W. Shen, James S. Blomgren |
1998-08-04 |
| 5687336 |
Stack push/pop tracking and pairing in a pipelined processor |
Gene W. Shen, James S. Blomgren |
1997-11-11 |
| 5632028 |
Hardware support for fast software emulation of unimplemented instructions |
Farnad Sajjadian, Jaspal Kohli, Niteen A. Patkar |
1997-05-20 |