Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11775429 | NUMA-aware garbage collection | Antonios Printezis, Igor Veresov, John Coomes | 2023-10-03 |
| 11748260 | Service performance enhancement using advance notifications of reduced-capacity phases of operations | James Christopher Sorenson, III, Yishai Galatzer, Bernd Joachim Wolfgang Mathiske, Steven Collison | 2023-09-05 |
| 11099982 | NUMA-aware garbage collection | Antonios Printezis, Igor Veresov, John Coomes | 2021-08-24 |
| 10963376 | NUMA-aware garbage collection | Antonios Printezis, Igor Veresov, John Coomes | 2021-03-30 |
| 10140208 | NUMA-aware garbage collection | Antonios Printezis, Igor Veresov, John Coomes | 2018-11-27 |
| 9910646 | Technologies for native code invocation using binary analysis | Abhay S. Kanhere, Haitao Feng, Aravind Subramanian | 2018-03-06 |
| 8972629 | Low-contention update buffer queuing for large systems | Antonios Printezis | 2015-03-03 |
| 8782306 | Low-contention update buffer queuing for large systems | Antonios Printezis | 2014-07-15 |
| 8683483 | Resource utilization monitor | — | 2014-03-25 |
| 8645651 | Low-contention update buffer queuing for small systems | Antonios Printezis | 2014-02-04 |
| 8121828 | Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions | John S. Yates, Jr., David L. Reese, Stephen C. Purcell, Korbin S. Van Dyke | 2012-02-21 |
| 8074055 | Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code | John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke, Tiruvur R. Ramesh | 2011-12-06 |
| 8065504 | Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor | John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke, Shalesh Thusoo, Tiruvur R. Ramesh | 2011-11-22 |
| 7941647 | Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination | John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke, T. R. Ramesh | 2011-05-10 |
| 7254806 | Detecting reordered side-effects | John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke | 2007-08-07 |
| 7137110 | Profiling ranges of execution of a computer program | David L. Reese, John S. Yates, Jr. | 2006-11-14 |
| 7111290 | Profiling program execution to identify frequently-executed portions and to assist binary translation | John S. Yates, Jr., David L. Reese | 2006-09-19 |
| 7069421 | Side tables annotating an instruction stream | John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke, T. R. Ramesh | 2006-06-27 |
| 7013456 | Profiling execution of computer programs | Korbin S. Van Dyke, David L. Reese, John S. Yates, Jr., T. R. Ramesh, Shalesh Thusoo +3 more | 2006-03-14 |
| 6978462 | Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled | Michael C. Adler, John S. Yates, Jr., David L. Reese, Stephen C. Purcell | 2005-12-20 |
| 6941545 | Profiling of computer programs executing in virtual memory systems | David L. Reese, John S. Yates, Jr., Korbin S. Van Dyke, T. R. Ramesh, Shalesh Thusoo +2 more | 2005-09-06 |
| 6826748 | Profiling program execution into registers of a computer | David L. Reese, John S. Yates, Jr., Korbin S. Van Dyke, T. R. Ramesh, Shalesh Thusoo +2 more | 2004-11-30 |
| 6789181 | Safety net paradigm for managing two computer execution modes | John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke | 2004-09-07 |
| 6763452 | Modifying program execution based on profiling | John S. Yates, Jr., Korbin S. Van Dyke, David L. Reese, Stephen C. Purcell | 2004-07-13 |
| 6064815 | System and method for generating fix-up code facilitating avoidance of an exception of a predetermined type in a digital computer system | David L. Reese | 2000-05-16 |