| 6076155 |
Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets |
James S. Blomgren |
2000-06-13 |
| 5848264 |
Debug and video queue for multi-processor chip |
Brian R. Baird, Shalesh Thusoo, David Matthew James Stark, James S. Blomgren |
1998-12-08 |
| 5805918 |
Dual-instruction-set CPU having shared register for storing data before switching to the alternate instruction set |
James S. Blomgren |
1998-09-08 |
| 5781457 |
Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU |
Earl T. Cohen, James S. Blomgren |
1998-07-14 |
| 5781750 |
Dual-instruction-set architecture CPU with hidden software emulation mode |
James S. Blomgren |
1998-07-14 |
| 5685009 |
Shared floating-point registers and register port-pairing in a dual-architecture CPU |
James S. Blomgren, Cheryl Senter Brashears |
1997-11-04 |
| 5664159 |
Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register |
James S. Blomgren |
1997-09-02 |
| 5652872 |
Translator having segment bounds encoding for storage in a TLB |
James S. Blomgren |
1997-07-29 |
| 5598553 |
Program watchpoint checking using paging with sub-page validity |
Earl T. Cohen, James S. Blomgren |
1997-01-28 |
| 5481693 |
Shared register architecture for a dual-instruction-set CPU |
James S. Blomgren |
1996-01-02 |
| 5481684 |
Emulating operating system calls in an alternate instruction set using a modified code segment descriptor |
Jay C. Pattin, James S. Blomgren |
1996-01-02 |
| 5455909 |
Microprocessor with operation capture facility |
James S. Blomgren, Jimmy Bracking, Francis J. Spahn |
1995-10-03 |
| 5440710 |
Emulation of segment bounds checking using paging with sub-page validity |
Earl T. Cohen, James S. Blomgren |
1995-08-08 |
| 5274791 |
Microprocessor with OEM mode for power management with input/output intiated selection of special address space |
Jimmy Bracking, James S. Blomgren |
1993-12-28 |