Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12086919 | Video pipeline | Arthur Y. Zhang, Ray L. Chang, Timothy R. Oriol, Ling Su, Guy Cote +7 more | 2024-09-10 |
| 11804019 | Media compositor for computer-generated reality | Ranjit Desai, Venu M. Duggineni, Perry A. Caro, Alexsandr M. Movshovich | 2023-10-31 |
| 11727619 | Video pipeline | Arthur Y. Zhang, Ray L. Chang, Timothy R. Oriol, Ling Su, Guy Cote +7 more | 2023-08-15 |
| 11308696 | Media compositor for computer-generated reality | Ranjit Desai, Venu M. Duggineni, Perry A. Caro, Aleksandr Movshovich | 2022-04-19 |
| 11043018 | Video pipeline | Arthur Y. Zhang, Ray L. Chang, Timothy R. Oriol, Ling Su, Guy Cote +7 more | 2021-06-22 |
| 10802968 | Processor to memory with coherency bypass | Sukalpa Biswas, Harshavardhan Kaushikkar, Munetoshi Fukami, Manu Gulati, Shinye Shiu | 2020-10-13 |
| 10102131 | Proactive power management for data storage devices to reduce access latency | Peter F. Holland | 2018-10-16 |
| 10102607 | Method for chaining media processing | Timothy J. Millet, Manu Gulati, Arthur L. Spence, Robert P. Esser | 2018-10-16 |
| 9891853 | Memory calibration abort | Neeraj Parik, Rakesh L. Notani, Robert E. Jeter | 2018-02-13 |
| 9779468 | Method for chaining media processing | Timothy J. Millet, Manu Gulati, Arthur L. Spence, Robert P. Esser | 2017-10-03 |
| 9639143 | Interfacing dynamic hardware power managed blocks and software power managed blocks | Erik P. Machnicki, Munetoshi Fukami, Shane J. Keil, Chaitanya Kosaraju, Erdem Guleyupoglu +2 more | 2017-05-02 |
| 9524261 | Credit lookahead mechanism | Harshavardhan Kaushikkar, Benjamin K. Dodge | 2016-12-20 |
| 9495318 | Synchronizing transactions for a single master over multiple busses | Deniz Balkan, Jim Jian Lin, Timothy R. Paaske, Ben D. Jarrett | 2016-11-15 |
| 9367474 | Translating cache hints | Shailendra Desai, Deniz Balkan, James Wang | 2016-06-14 |
| 9317102 | Power control for cache structures | Muditha Kanchana, Harshavardhan Kaushikkar, Erik P. Machnicki, Seye Ewedemi | 2016-04-19 |
| 9310783 | Dynamic clock and power gating with decentralized wake-ups | Erik P. Machnicki, Munetoshi Fukami, Shane J. Keil | 2016-04-12 |
| 9280471 | Mechanism for sharing private caches in a SoC | Manu Gulati, Harshavardhan Kaushikkar, Wei-Han Lien, Gerard R. Williams, III, Sukalpa Biswas +2 more | 2016-03-08 |
| 9280503 | Round robin arbiter handling slow transaction sources and preventing block | Deniz Balkan, Munetoshi Fukami | 2016-03-08 |
| 9270610 | Apparatus and method for controlling transaction flow in integrated circuits | Deniz Balkan, Kevin C. Wong, Munetoshi Fukami | 2016-02-23 |
| 9229896 | Systems and methods for maintaining an order of read and write transactions in a computing system | Deniz Balkan | 2016-01-05 |
| 9229894 | Protocol conversion involving multiple virtual channels | Deniz Balkan, Joseph P. Bratt, Kevin C. Wong, Manu Gulati, Rohit Gupta | 2016-01-05 |
| 9201791 | Flow-ID dependency checking logic | Harshavardhan Kaushikkar | 2015-12-01 |
| 9189435 | Method and apparatus for arbitration with multiple source paths | Benjamin K. Dodge, Deniz Balkan, Munetoshi Fukami | 2015-11-17 |
| 9182811 | Interfacing dynamic hardware power managed blocks and software power managed blocks | Erik P. Machnicki, Munetoshi Fukami, Shane J. Keil, Chaitanya Kosaraju, Erdem Guleyupoglu +2 more | 2015-11-10 |
| 9170768 | Managing fast to slow links in a bus fabric | Jason M. Kassoff, Kevin C. Wong, Brian P. Lilly | 2015-10-27 |