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Application aware SoC memory cache partitioning |
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Parallel coherence and memory cache processing pipelines |
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Cache drop feature to increase memory bandwidth and save power |
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Cache drop feature to increase memory bandwidth and save power |
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| 9823730 |
Power management of cache duplicate tags |
Erik P. Machnicki |
2017-11-21 |
| 9454482 |
Duplicate tag structure employing single-port tag RAM and dual-port state RAM |
Harshavardhan Kaushikkar, Odutola Oluseye Ewedemi |
2016-09-27 |
| 9317102 |
Power control for cache structures |
Gurjeet S. Saund, Harshavardhan Kaushikkar, Erik P. Machnicki, Seye Ewedemi |
2016-04-19 |
| 9176913 |
Coherence switch for I/O traffic |
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2015-04-28 |
