BL

Brian P. Lilly

Apple: 37 patents #795 of 18,612Top 5%
HP HP: 4 patents #3,523 of 16,619Top 25%
UN Unknown: 2 patents #12,644 of 83,584Top 20%
Overall (All Time): #66,409 of 4,157,543Top 2%
44
Patents All Time

Issued Patents All Time

Showing 25 most recent of 44 patents

Patent #TitleCo-InventorsDate
12332792 Scalable cache coherency protocol James Vash, Gaurav Garg, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2025-06-17
12216578 Request ordering in a cache Sandeep Gupta, Krishna C. Potnuru 2025-02-04
11947457 Scalable cache coherency protocol James Vash, Gaurav Garg, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2024-04-02
11893241 Variable hit latency cache Sandeep Gupta, Chandan Shantharaj, Krishna C. Potnuru, Sahil Kapoor 2024-02-06
11868258 Scalable cache coherency protocol James Vash, Gaurav Garg, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2024-01-09
11768690 Coprocessor context priority Aditya Kesiraju, Andrew J. Beaumont-Smith, James Vash, Jason M. Kassoff, Krishna C. Potnuru +4 more 2023-09-26
11741009 Request ordering in a cache Sandeep Gupta, Krishna C. Potnuru 2023-08-29
11544193 Scalable cache coherency protocol James Vash, Gaurav Garg, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2023-01-03
11210104 Coprocessor context priority Aditya Kesiraju, Andrew J. Beaumont-Smith, James Vash, Jason M. Kassoff, Krishna C. Potnuru +4 more 2021-12-28
11138111 Parallel coherence and memory cache processing pipelines Muditha Kanchana, Srinivasa Rangan Sridharan, Harshavardhan Kaushikkar, Sridhar Kotha 2021-10-05
10795818 Method and apparatus for ensuring real-time snoop latency Harshavardhan Kaushikkar, Per Hammarlund, Michael Bekerman, James Vash, Manu Gulati +1 more 2020-10-06
9563575 Least recently used mechanism for cache line eviction from a cache memory Gerard R. Williams, III, Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Hari Kannan, Prashant Jain 2017-02-07
9563567 Selective cache way-group power down Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Hari Kannan 2017-02-07
9529730 Methods for cache line eviction Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Hari Kannan 2016-12-27
9513693 L2 cache retention mode Prashant Jain, Mahnaz Sadoughi-Yarandi, Helen-Xing Huang 2016-12-06
9454486 Cache pre-fetch merge in pending request buffer Perumal R. Subramoniam, Prashant Jain 2016-09-27
9381401 Range of motion machine and method and adjustable crank David L. Lampert, Stephen John Briggs, Edward William Cler, Daniel David Horein, Benjamin Berton Rund 2016-07-05
9352189 Range of motion machine and method and adjustable crank David L. Lampert, Stephen John Briggs, Edward William Cler, Daniel David Horein, Benjamin Berton Rund 2016-05-31
9298620 Selective victimization in a multi-level cache hierarchy Hari Kannan, Perumal R. Subramoniam 2016-03-29
9280471 Mechanism for sharing private caches in a SoC Manu Gulati, Harshavardhan Kaushikkar, Gurjeet S. Saund, Wei-Han Lien, Gerard R. Williams, III +2 more 2016-03-08
9229866 Delaying cache data array updates Hari Kannan, Perumal R. Subramoniam, Pradeep Kanapathipillai 2016-01-05
9176879 Least recently used mechanism for cache line eviction from a cache memory Gerard R. Williams, III, Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Hari Kannan, Prashant Jain 2015-11-03
9170768 Managing fast to slow links in a bus fabric Jason M. Kassoff, Kevin C. Wong, Gurjeet S. Saund 2015-10-27
9152210 Method and apparatus for determining tunable parameters to use in power and performance management Erik P. Machnicki, Gurjeet S. Saund, Sukalpa Biswas 2015-10-06
9128857 Flush engine Gerard R. Williams, III 2015-09-08