Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9563567 | Selective cache way-group power down | Perumal R. Subramonium, Brian P. Lilly, Hari Kannan | 2017-02-07 |
| 9563575 | Least recently used mechanism for cache line eviction from a cache memory | Brian P. Lilly, Gerard R. Williams, III, Perumal R. Subramonium, Hari Kannan, Prashant Jain | 2017-02-07 |
| 9529730 | Methods for cache line eviction | Perumal R. Subramonium, Brian P. Lilly, Hari Kannan | 2016-12-27 |
| 9513693 | L2 cache retention mode | Prashant Jain, Brian P. Lilly, Helen-Xing Huang | 2016-12-06 |
| 9176879 | Least recently used mechanism for cache line eviction from a cache memory | Brian P. Lilly, Gerard R. Williams, III, Perumal R. Subramonium, Hari Kannan, Prashant Jain | 2015-11-03 |
| 9098418 | Coordinated prefetching based on training in hierarchically cached processors | Hari Kannan, Brian P. Lilly, Gerard R. Williams, III, Perumal R. Subramoniam, Pradeep Kanapathipillai | 2015-08-04 |
| 9047198 | Prefetching across page boundaries in hierarchically cached processors | Hari Kannan, Pradeep Kanapathipillai, Brian P. Lilly, Perumal R. Subramoniam | 2015-06-02 |