Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12242855 | Coprocessor operation bundling | Brett S. Feero, Nikhil Gupta, Viney Gautam | 2025-03-04 |
| 12174785 | Coprocessors with bypass optimization, variable grid architecture, and fused vector operations | Andrew J. Beaumont-Smith, Boris S. Alvarez-Heredia, Pradeep Kanapathipillai, Ran A. Chachick | 2024-12-24 |
| 12135681 | Coprocessors with bypass optimization, variable grid architecture, and fused vector operations | Andrew J. Beaumont-Smith, Boris S. Alvarez-Heredia, Ran A. Chachick | 2024-11-05 |
| 11775301 | Coprocessor register renaming using registers associated with an inactive context to store results from an active context | Ran A. Chachick, Andrew J. Beaumont-Smith, Jong-Suk Lee | 2023-10-03 |
| 11768690 | Coprocessor context priority | Andrew J. Beaumont-Smith, Brian P. Lilly, James Vash, Jason M. Kassoff, Krishna C. Potnuru +4 more | 2023-09-26 |
| 11755328 | Coprocessor operation bundling | Brett S. Feero, Nikhil Gupta, Viney Gautam | 2023-09-12 |
| 11650825 | Coprocessor synchronizing instruction suppression | Rajdeep L. Bhuyar, Ran A. Chachick, Andrew J. Beaumont-Smith | 2023-05-16 |
| 11500638 | Hardware compression and decompression engine | James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Zhaoming Hu, Tyler J. Huberty +1 more | 2022-11-15 |
| 11429555 | Coprocessors with bypass optimization, variable grid architecture, and fused vector operations | Andrew J. Beaumont-Smith, Boris S. Alvarez-Heredia, Srikanth Balasubramanian | 2022-08-30 |
| 11249766 | Coprocessor synchronizing instruction suppression | Rajdeep L. Bhuyar, Ran A. Chachick, Andrew J. Beaumont-Smith | 2022-02-15 |
| 11210104 | Coprocessor context priority | Andrew J. Beaumont-Smith, Brian P. Lilly, James Vash, Jason M. Kassoff, Krishna C. Potnuru +4 more | 2021-12-28 |
| 11210100 | Coprocessor operation bundling | Brett S. Feero, Nikhil Gupta, Viney Gautam | 2021-12-28 |
| 11055102 | Coprocessor memory ordering table | Brett S. Feero, Nikhil Gupta | 2021-07-06 |
| 10970077 | Processor with multiple load queues including a queue to manage ordering and a queue to manage replay | Mridul Agarawal, Nikhil Gupta | 2021-04-06 |
| 10969858 | Operation processing controlled according to difference in current consumption | Daniel U. Becker, Srikanth Balasubramanian, Venkatram Krishnaswamy, Boris S. Alvarez-Heredia | 2021-04-06 |
| 10846091 | Coprocessor with distributed register | Andrew J. Beaumont-Smith, Deepankar Duggal, Ran A. Chachick | 2020-11-24 |
| 10776125 | Coprocessor memory ordering table | Brett S. Feero, Nikhil Gupta | 2020-09-15 |
| 10628164 | Branch resolve pointer optimization | Kulin N. Kothari, Mridul Agarwal, Deepankar Duggal, Sean M. Reynolds | 2020-04-21 |
| 10318427 | Resolving memory accesses crossing cache line boundaries | Ramon Matas, Chung-Lun Chan, Alexey P. Suprun | 2019-06-11 |
| 10133571 | Load-store unit with banked queue | Mridul Agarwal, Pradeep Kanapathipillai, Sean M. Reynolds | 2018-11-20 |
| 9886396 | Scalable event handling in multi-threaded processor cores | Roger Gramunt, Rammohan Padmanabhan, Ramon Matas, Neal S. Moyer, Benjamin Crawford Chaffin +7 more | 2018-02-06 |
| 9715432 | Memory fault suppression via re-execution and hardware FSM | Ramon Matas, Roger Gramunt, Chung-Lun Chan, Benjamin Crawford Chaffin, Jonathan C. Hall +1 more | 2017-07-25 |