Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9098418 | Coordinated prefetching based on training in hierarchically cached processors | Hari Kannan, Gerard R. Williams, III, Mahnaz Sadoughi-Yarandi, Perumal R. Subramoniam, Pradeep Kanapathipillai | 2015-08-04 |
| 9047198 | Prefetching across page boundaries in hierarchically cached processors | Hari Kannan, Pradeep Kanapathipillai, Perumal R. Subramoniam, Mahnaz Sadoughi-Yarandi | 2015-06-02 |
| 9044630 | Range of motion machine and method and adjustable crank | David L. Lampert, Stephen John Briggs, Edward William Cler, Daniel David Horein, Benjamin Berton Rund | 2015-06-02 |
| 9043554 | Cache policies for uncacheable memory requests | Gerard R. Williams, III, Perumal R. Subramoniam, Pradeep Kanapathipillai | 2015-05-26 |
| 8751746 | QoS management in the L2 cache | — | 2014-06-10 |
| 8713277 | Critical word forwarding with adaptive prediction | Jason M. Kassoff, Hao Chen | 2014-04-29 |
| 8566528 | Combining write buffer with dynamically adjustable flush metrics | Peter J. Bannon, Andrew J. Beaumont-Smith, Ramesh Gunna, Wei-Han Lien, Jaidev P. Patwardhan +2 more | 2013-10-22 |
| 8458406 | Multiple critical word bypassing in a memory controller | Sukalpa Biswas, Hao Chen | 2013-06-04 |
| 8352685 | Combining write buffer with dynamically adjustable flush metrics | Peter J. Bannon, Andrew J. Beaumont-Smith, Ramesh Gunna, Wei-Han Lien, Jaidev P. Patwardhan +2 more | 2013-01-08 |
| 8347040 | Latency reduction for cache coherent bus-based cache | Sridhar Subramanian, Ramesh Gunna | 2013-01-01 |
| 8219880 | Combined single error correction/device kill detection code | Robert Gries, Sridhar Subramanian, Sukalpa Biswas, Hao Chen | 2012-07-10 |
| 8055975 | Combined single error correction/device kill detection code | Robert Gries, Sridhar Subramanian, Sukalpa Biswas, Hao Chen | 2011-11-08 |
| 8036061 | Integrated circuit with multiported memory supercell and data path switching circuitry | Shinye Shiu | 2011-10-11 |
| 7949832 | Latency reduction for cache coherent bus-based cache | Sridhar Subramanian, Ramesh Gunna | 2011-05-24 |
| 7702858 | Latency reduction for cache coherent bus-based cache | Sridhar Subramanian, Ramesh Gunna | 2010-04-20 |
| 7370151 | Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache | David Asher, Joel Grodstein, Patrick FitzGerald | 2008-05-06 |
| 6681295 | Fast lane prefetching | Stephen C. Root, Richard E. Kessler, David Asher | 2004-01-20 |
| 6671822 | Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache | David Asher, Joel Grodstein, Patrick FitzGerald | 2003-12-30 |
| 6654858 | Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol | David Asher, Richard E. Kessler, Michael Bertone | 2003-11-25 |