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Inter cluster snoop latency reduction |
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2022-12-27 |
| 11016913 |
Inter cluster snoop latency reduction |
Harshavardhan Kaushikkar, Christopher D. Shuler, Srinivasa Rangan Sridharan, Yu Zhang, Kaushik Kannan |
2021-05-25 |
| 10963172 |
Systems and methods for providing a back pressure free interconnect |
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2021-03-30 |
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Systems and methods for controlling data on a bus using latency |
Shawn Munetoshi Fukami, Yiu Chun Tse, David L. Trawick, Hengsheng Geng, Jaideep Dastidar +1 more |
2019-09-24 |
| 10324865 |
Maintaining ordering requirements while converting protocols in a communications fabric |
— |
2019-06-18 |
| 10255218 |
Systems and methods for maintaining specific ordering in bus traffic |
Yiu Chun Tse, Vinodh R. Cuppu, Shawn Munetoshi Fukami, Jaideep Dastidar, Hengsheng Geng |
2019-04-09 |
| 9647653 |
Method for reduced power clock frequency monitoring |
Shu-Yi Yu, Jean-Didier Allegrucci, Timothy R. Paaske |
2017-05-09 |
| 9495318 |
Synchronizing transactions for a single master over multiple busses |
Gurjeet S. Saund, Jim Jian Lin, Timothy R. Paaske, Ben D. Jarrett |
2016-11-15 |
| 9367474 |
Translating cache hints |
Shailendra Desai, Gurjeet S. Saund, James Wang |
2016-06-14 |
| 9280503 |
Round robin arbiter handling slow transaction sources and preventing block |
Gurjeet S. Saund, Munetoshi Fukami |
2016-03-08 |
| 9270610 |
Apparatus and method for controlling transaction flow in integrated circuits |
Gurjeet S. Saund, Kevin C. Wong, Munetoshi Fukami |
2016-02-23 |
| 9229894 |
Protocol conversion involving multiple virtual channels |
Gurjeet S. Saund, Joseph P. Bratt, Kevin C. Wong, Manu Gulati, Rohit Gupta |
2016-01-05 |
| 9229896 |
Systems and methods for maintaining an order of read and write transactions in a computing system |
Gurjeet S. Saund |
2016-01-05 |
| 9189435 |
Method and apparatus for arbitration with multiple source paths |
Benjamin K. Dodge, Gurjeet S. Saund, Munetoshi Fukami |
2015-11-17 |
| 9152588 |
Race-free level-sensitive interrupt delivery using fabric delivered interrupts |
Manu Gulati, Erik P. Machnicki |
2015-10-06 |
| 9135202 |
Bridge circuit for bus protocol conversion and error handling |
Gurjeet S. Saund, Shu-Yi Yu |
2015-09-15 |
| 9053058 |
QoS inband upgrade |
Gurjeet S. Saund, Kevin C. Wong |
2015-06-09 |
| 9009377 |
Edge-triggered interrupt conversion in a system employing level-sensitive interrupts |
Erik P. Machnicki, Manu Gulati |
2015-04-14 |
| 8949756 |
Debug access with programmable return clock |
Kevin R. Walker, Mitchell P. Lichtenberg |
2015-02-03 |
| 8806232 |
Systems and method for hardware dynamic cache power management via bridge and power manager |
Timothy J. Millet, Erik P. Machnicki, Vijay Gupta |
2014-08-12 |
| 8793411 |
Bridge circuit reorder buffer for transaction modification and translation |
Gurjeet S. Saund |
2014-07-29 |
| 8769239 |
Re-mapping memory transactions |
Gurjeet S. Saund |
2014-07-01 |
| 8694830 |
Debug registers for halting processor cores after reset or power off |
Kevin R. Walker, Mitchell P. Lichtenberg |
2014-04-08 |
| 8607022 |
Processing quality-of-service (QoS) information of memory transactions |
Gurjeet S. Saund, Vijay Gupta |
2013-12-10 |
| 8402314 |
Debug registers for halting processor cores after reset or power off |
Kevin R. Walker, Mitchell P. Lichtenberg |
2013-03-19 |
