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John Szeto — 8 Patents

HSHal Computer Systems: 6 patents #4 of 34Top 15%
Fujitsu Limited: 2 patents #10,930 of 24,456Top 45%
Oakland, CA: #802 of 4,380 inventorsTop 20%
California: #74,834 of 386,348 inventorsTop 20%
Overall (All Time): #600,572 of 4,157,543Top 15%
8 Patents All Time
John Szeto has been granted 8 US patents while listed as an inventor at Hal Computer Systems. The first was granted in 1997 and the most recent in October 1999. John Szeto ranks #600,572 of 4,157,543 US inventors in our database (top 14.4%). Patent records list John Szeto in Oakland, CA, US.

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
5966530 Structure and method for instruction boundary machine state restoration Gene W. Shen, Niteen A. Patkar, Michael C. Shebanow 1999-10-12
5751985 Processor structure and method for tracking instruction status to maintain precise state Gene W. Shen, Niteen A. Patkar, Michael C. Shebanow 1998-05-12
5745726 Method and apparatus for selecting the oldest queued instructions without data dependencies Michael C. Shebanow, John Gmuender, Michael A. Simone, Takumi Maruyama, DeForest Tovey 1998-04-28
5673426 Processor structure and method for tracking floating-point exceptions Gene W. Shen, Michael C. Shebanow 1997-09-30
5659721 Processor structure and method for checkpointing instructions to maintain precise state Gene W. Shen, Niteen A. Patkar, Michael C. Shebanow 1997-08-19
5651124 Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state Gene W. Shen, Niteen A. Patkar, Michael C. Shebanow, Michael A. Simone 1997-07-22
5649136 Processor structure and method for maintaining and restoring precise state at any instruction boundary Gene W. Shen, Niteen A. Patkar, Michael C. Shebanow 1997-07-15
5644742 Processor structure and method for a time-out checkpoint Gene W. Shen, Niteen A. Patkar, Michael C. Shebanow 1997-07-01