Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386624 | Invariant statistics-based configuration of processor components | Alok Garg, Mayank Chhablani, Furkan Eris | 2025-08-12 |
| 12050916 | Array of pointers prefetching | Chetana N. Keltcher, Alok Garg | 2024-07-30 |
| 12045169 | Hardware configuration selection using machine learning model | Furkan Eris, John Kalamatianos, Mayank Chhablani, Alok Garg | 2024-07-23 |
| 11455252 | Multi-class multi-label classification using clustered singular decision trees for hardware adaptation | John Kalamatianos, Mayank Chhablani, Alok Garg, Furkan Eris | 2022-09-27 |
| 10255070 | ISA extensions for synchronous coalesced accesses | David Whelihan | 2019-04-09 |
| 9026739 | Multimode prefetcher | Srilatha Manne, Nitya Ranganathan, Donald W. McCauley | 2015-05-05 |
| 7774578 | Apparatus and method of prefetching data in response to a cache miss | — | 2010-08-10 |
| 7139897 | Computer instruction dispatch | Gary L. Vondran, Jr. | 2006-11-21 |
| 7051300 | Method and system for architectural power estimation | Gene W. Shen, Stephan G. Meier, Leslie Barnes | 2006-05-23 |
| 6915402 | Method and system for creating secure address space using hardware memory router | Kenneth Mark Wilson, Yoshio Turner | 2005-07-05 |
| 6874014 | Chip multiprocessor with multiple operating systems | Stephen Richardson, Gary L. Vondran, Jr., Stuart Siu, Shankar Venkataraman, Padmanabha Venkitakrishnan +1 more | 2005-03-29 |
| 6782453 | Storing data in memory | Stephen Richardson | 2004-08-24 |
| 6779100 | Method and device for address translation for compressed instructions | Stephen Richardson | 2004-08-17 |
| 6314494 | Dynamically size configurable data buffer for data cache and prefetch cache memory | Jeanne M Hermsen | 2001-11-06 |