GM

Graham Ricketson Murphy

Oracle: 15 patents #683 of 14,854Top 5%
Motorola: 2 patents #4,475 of 12,470Top 40%
IBM: 2 patents #32,839 of 70,183Top 50%
Overall (All Time): #277,429 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8756363 Efficient storage of memory version data Zoran Radovic, Bharat Daga 2014-06-17
8751736 Instructions to set and read memory version information Zoran Radovic, Darryl J. Gove 2014-06-10
8732430 Method and apparatus for using unused bits in a memory pointer Zoran Radovic, Paul J. Jordan, John G. Johnson 2014-05-20
8370576 Cache rollback acceleration via a bank based versioning cache ciruit John G. Favor, Paul G. Chan, Joseph B. Rowlands 2013-02-05
8370609 Data cache rollbacks for failed speculative traces with memory operations John G. Favor, Paul G. Chan, Joseph B. Rowlands 2013-02-05
8051247 Trace based deallocation of entries in a versioning cache circuit John G. Favor, Paul G. Chan, Joseph B. Rowlands 2011-11-01
8024522 Memory ordering queue/versioning cache circuit John G. Favor, Paul G. Chan, Joseph B. Rowlands 2011-09-20
8019944 Checking for a memory ordering violation after a speculative cache write John G. Favor, Paul G. Chan, Joseph B. Rowlands 2011-09-13
8010745 Rolling back a speculative update of a non-modifiable cache line John G. Favor, Paul G. Chan, Joseph B. Rowlands 2011-08-30
7877630 Trace based rollback of a speculatively updated cache John G. Favor, Paul G. Chan, Joseph B. Rowlands 2011-01-25
7779307 Memory ordering queue tightly coupled with a versioning cache circuit John G. Favor, Paul G. Chan, Joseph B. Rowlands 2010-08-17
6499097 Instruction fetch unit aligner for a non-power of two size VLIW instruction Marc Tremblay, Frank C. Chiu 2002-12-24
6321325 Dual in-line buffers for an instruction fetch unit Marc Tremblay 2001-11-20
6314509 Efficient method for fetching instructions having a non-power of two size Marc Tremblay 2001-11-06
6249861 Instruction fetch unit aligner for a non-power of two size VLIW instruction Marc Tremblay, Frank C. Chiu 2001-06-19
5664215 Data processor with an execution unit for performing load instructions and method of operation David P. Burgess, Marvin Denman, Milton M. Hood, Jr., Mark A. Kearney, Lavanya Kling +1 more 1997-09-02
5621896 Data processor with unified store queue permitting hit under miss memory accesses David P. Burgess, Milton M. Hood, Jr., Betty Y. Kikuta 1997-04-15