PC

Paul G. Chan

Oracle: 9 patents #1,297 of 14,854Top 9%
IN Intel: 4 patents #8,473 of 30,777Top 30%
HP HP: 4 patents #1,237 of 7,018Top 20%
SM Soft Machines: 1 patents #3 of 5Top 60%
Overall (All Time): #254,299 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10552334 Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early Karthikeyan Avudaiyappan 2020-02-04
10402322 Systems and methods for faster read after write forwarding using a virtual address Karthikeyan Avudaiyappan 2019-09-03
9767020 Systems and methods for faster read after write forwarding using a virtual address Karthikeyan Avudaiyappan 2017-09-19
9632947 Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early Karthikeyan Avudaiyappan 2017-04-25
9361227 Systems and methods for faster read after write forwarding using a virtual address Karthikeyan Avudaiyappan 2016-06-07
8370609 Data cache rollbacks for failed speculative traces with memory operations John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2013-02-05
8370576 Cache rollback acceleration via a bank based versioning cache ciruit John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2013-02-05
8051247 Trace based deallocation of entries in a versioning cache circuit John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2011-11-01
8024522 Memory ordering queue/versioning cache circuit John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2011-09-20
8019944 Checking for a memory ordering violation after a speculative cache write John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2011-09-13
8010745 Rolling back a speculative update of a non-modifiable cache line John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2011-08-30
7877630 Trace based rollback of a speculatively updated cache John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2011-01-25
7779307 Memory ordering queue tightly coupled with a versioning cache circuit John G. Favor, Graham Ricketson Murphy, Joseph B. Rowlands 2010-08-17
7644221 System interface unit Ricky C. Hetherington 2010-01-05
5375242 Compiler architecture for cross-module optimization Rajiv Kumar 1994-12-20
5339419 ANDF compiler using the HPcode-plus compiler intermediate language Manoj Dadoo, Karl Pettis, Vatsa Santhanan 1994-08-16
5280613 ANDF installer using the HPcode-Plus compiler intermediate language Manoj Dadoo, Karl Pettis, Vatsa Santhanan 1994-01-18
5276881 ANDF producer using the HPcode-Plus compiler intermediate language Manoj Dadoo, Karl Pettis, Vatsa Santhanam 1994-01-04