BB

Bryan Black

IN Intel: 15 patents #2,741 of 30,777Top 9%
Motorola: 5 patents #2,124 of 12,470Top 20%
IBM: 2 patents #32,839 of 70,183Top 50%
Overall (All Time): #208,846 of 4,157,543Top 6%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9977674 Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instruction Jeffrey P. Rupley, II, Edward A. Brekelbaum, Edward T. Grochowski 2018-05-22
8860199 Multi-die processor Nicholas Samra, M. Clair Webb 2014-10-14
8110899 Method for incorporating existing silicon die into 3D integrated stack Paul A. Reed 2012-02-07
8059441 Memory array on more than one die Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum +2 more 2011-11-15
8032711 Prefetching from dynamic random access memory to a static random access memory Murali Annavaram, Donald W. McCauley, John P. DeVale 2011-10-04
7692946 Memory array on more than one die Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum +2 more 2010-04-06
7620781 Efficient Bloom filter Mauricio Breternitz, Youfeng Wu, Peter G. Sassone, Jeffrey P. Rupley, II, Wesley Attrot 2009-11-17
7428631 Apparatus and method using different size rename registers for partial-bit and bulk-bit writes Jeffrey P. Rupley, II, Edward A. Brekelbaum 2008-09-23
7418551 Multi-purpose register cache John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II 2008-08-26
7228402 Predicate register file write by an instruction with a pending instruction having data dependency Bohuslav Rychlik, Ryan Rakvic, Edward A. Brekelbaum 2007-06-05
7171545 Predictive filtering of register cache entry John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II 2007-01-30
7130990 Efficient instruction scheduling with lossy tracking of scheduling information Edward A. Brekelbaum, Jeffrey P. Rupley, II 2006-10-31
7120749 Cache mechanism Ryan Rakvic, Youfeng Wu, John Shen 2006-10-10
6954848 Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately Ryan Rakvic, Christopher B. Wilkerson, Edward T. Grochowski, John Shen, Edward A. Brekelbaum 2005-10-11
6928645 Software-based speculative pre-computation and multithreading Hong Wang, Jamison D. Collins, John Shen, Perry Wang, Edward T. Grochowski +1 more 2005-08-09
5805877 Data processor with branch target address cache and method of operation Marvin Denman, Seungyoon Peter Song 1998-09-08
5761723 Data processor with branch prediction and method of operation Marvin Denman, Mark A. Kearney, Seungyoon Peter Song 1998-06-02
5717587 Method and system for recording noneffective instructions within a data processing system Marvin Denman, Lee Evan Eisen, Robert T. Golla, Albert J. Loper, Soummya Mallick +1 more 1998-02-10
5619408 Method and system for recoding noneffective instructions within a data processing system Marvin Denman, Lee Evan Eisen, Robert T. Golla, Albert J. Loper, Soummya Mallick +1 more 1997-04-08
5613081 Method of operating a data processor with rapid address comparison for data forwarding Marvin Denman 1997-03-18
5530825 Data processor with branch target address cache and method of operation Marvin Denman 1996-06-25