Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8645772 | System and method for managing uncertain events for communication devices | Edward Glenn Howard, Thomas Hunter Cobbs, Tyler C. Poschel | 2014-02-04 |
| 8110899 | Method for incorporating existing silicon die into 3D integrated stack | Bryan Black | 2012-02-07 |
| 5778432 | Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register | Lawrence H. Rubin | 1998-07-07 |
| 5765199 | Data processor with alocate bit and method of operation | Joseph Y. Chang, Hidayat Lioe, Brian Snider | 1998-06-09 |
| 5550774 | Memory cache with low power consumption and method of operation | Michael Brauer, John L. Duncan | 1996-08-27 |
| 5367655 | Memory and associated method including an operating mode for simultaneously selecting multiple rows of cells | Anita S. Grossman | 1994-11-22 |
| 5294847 | Latching sense amplifier | Anita S. Grossman | 1994-03-15 |
| 5130947 | Memory system for reliably writing addresses with reduced power consumption | — | 1992-07-14 |
| 4996641 | Diagnostic mode for a cache | Yoav Talgam, Elie I. Haddad, James Klingshirn | 1991-02-26 |
| 4818900 | Predecode and multiplex in addressing electrically programmable memory | Jeffrey M. Klass, Isam Rimawi | 1989-04-04 |
| 4716550 | High performance output driver | Stephen T. Flannagan | 1987-12-29 |
| 4698788 | Memory architecture with sub-arrays | Stephen T. Flannagan, John D. Barnes | 1987-10-06 |
| 4661931 | Asynchronous row and column control | Stephen T. Flannagan | 1987-04-28 |
| 4658381 | Bit line precharge on a column address change | Stephen T. Flannagan | 1987-04-14 |
| 4636991 | Summation of address transition signals | Stephen T. Flannagan | 1987-01-13 |
| 4630239 | Chip select speed-up circuit for a memory | Stephen T. Flannagan | 1986-12-16 |
| 4387447 | Column and ground select sequence in electrically programmable memory | Jeffrey M. Klaas, Isam Rimawi | 1983-06-07 |
| 4344154 | Programming sequence for electrically programmable memory | Jeffrey M. Klaas, Isam Rimawi | 1982-08-10 |
| 4314362 | Power down sequence for electrically programmable memory | Jeffrey M. Klaas, Isam Rimawi | 1982-02-02 |
| 4281397 | Virtual ground MOS EPROM or ROM matrix | Joseph H. Neal | 1981-07-28 |