Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6473349 | Cascode sense AMP and column select circuit and method of operation | — | 2002-10-29 |
| 6157583 | Integrated circuit memory having a fuse detect circuit and method therefor | Glenn E. Starnes, Ray L. Chang | 2000-12-05 |
| 6044036 | Buffer circuit, memory device, and integrated circuit for receiving digital signals | William R. Weier | 2000-03-28 |
| 6031408 | Square-law clamping circuit | — | 2000-02-29 |
| 5670815 | Layout for noise reduction on a reference voltage | Lawrence F. Childs, Ray L. Chang, Donovan Raatz | 1997-09-23 |
| 5610543 | Delay locked loop for detecting the phase difference of two signals having different frequencies | Ray L. Chang, Kenneth W. Jones | 1997-03-11 |
| 5485110 | ECL differential multiplexing circuit | Kenneth W. Jones | 1996-01-16 |
| 5477176 | Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory | Ray L. Chang, Lawrence F. Childs, Kenneth W. Jones, Donovan Raatz | 1995-12-19 |
| 5440515 | Delay locked loop for detecting the phase difference of two signals having different frequencies | Ray L. Chang, Kenneth W. Jones | 1995-08-08 |
| 5440514 | Write control for a memory using a delay locked loop | Ray L. Chang, Lawrence F. Childs | 1995-08-08 |
| 5426381 | Latching ECL to CMOS input buffer circuit | Lawrence F. Childs | 1995-06-20 |
| 5416744 | Memory having bit line load with automatic bit line precharge and equalization | Lawrence F. Childs | 1995-05-16 |
| 5402389 | Synchronous memory having parallel output data paths | Kenneth W. Jones, Roger I. Kung | 1995-03-28 |
| 5384737 | Pipelined memory having synchronous and asynchronous operating modes | Lawrence F. Childs, Kenneth W. Jones, Ray L. Chang | 1995-01-24 |
| 5293081 | Driver circuit for output buffers | Jennifer Chiao, Taisheng Feng | 1994-03-08 |
| 5287314 | BICMOS sense amplifier with reverse bias protection | Taisheng Feng | 1994-02-15 |
| 5268866 | Memory with column redundancy and localized column redundancy control signals | Tiasheng Feng, John D. Porter | 1993-12-07 |
| 5256917 | ECL logic gate with voltage protection | John D. Porter | 1993-10-26 |
| 5184033 | Regulated BiCMOS output buffer | Jennifer Chiao, Taisheng Feng | 1993-02-02 |
| 5173877 | BICMOS combined bit line load and write gate for a memory | Tai-Sheng Feng | 1992-12-22 |
| 5059829 | Logic level shifting circuit with minimal delay | Tai-Sheng Feng | 1991-10-22 |
| 5043602 | High speed logic circuit with reduced quiescent current | — | 1991-08-27 |
| 4964083 | Non-address transition detection memory with improved access time | Scott G. Nogle | 1990-10-16 |
| 4928268 | Memory using distributed data line loading | Scott G. Nogle, Perry H. Pelley, Bruce E. Engles | 1990-05-22 |
| 4807191 | Redundancy for a block-architecture memory | — | 1989-02-21 |