Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4807198 | Memory input buffer with hysteresis and dc margin | Peter Voss | 1989-02-21 |
| 4763303 | Write-drive data controller | — | 1988-08-09 |
| 4763306 | Circuit for enabling a transmission gate in response to predecoded signals | — | 1988-08-09 |
| 4716550 | High performance output driver | Paul A. Reed | 1987-12-29 |
| 4716302 | Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal | Lawrence Day, Barry Simon | 1987-12-29 |
| 4698788 | Memory architecture with sub-arrays | Paul A. Reed, John D. Barnes | 1987-10-06 |
| 4661931 | Asynchronous row and column control | Paul A. Reed | 1987-04-28 |
| 4658381 | Bit line precharge on a column address change | Paul A. Reed | 1987-04-14 |
| 4644197 | Reduced power sense amplifier | — | 1987-02-17 |
| 4644196 | Tri-state differential amplifier | — | 1987-02-17 |
| 4636991 | Summation of address transition signals | Paul A. Reed | 1987-01-13 |
| 4630239 | Chip select speed-up circuit for a memory | Paul A. Reed | 1986-12-16 |
| 4547867 | Multiple bit dynamic random-access memory | Edmund A. Reese, Dieter Spaderna | 1985-10-15 |
| 4468759 | Testing method and apparatus for dram | Roger I. Kung, Jonathan Spitz | 1984-08-28 |
| 4453237 | Multiple bit output dynamic random-access memory | Edmund A. Reese, Dieter Spaderna | 1984-06-05 |
| 4449207 | Byte-wide dynamic RAM with multiplexed internal buses | Roger I. Kung, Jonathan Spitz, Perry H. Pelley, Robert S. Riley, Douglas J. Covert | 1984-05-15 |
| 4406013 | Multiple bit output dynamic random-access memory | Edmund A. Reese, Dieter Spaderna | 1983-09-20 |