Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9564901 | Self-timed dynamic level shifter with falling edge generator | Daniel C. Chow, William R. Weier | 2017-02-07 |
| 8767495 | Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation | Edward M. McCombs, Daniel C. Chow, Alexander E. Runas | 2014-07-01 |
| 8570824 | Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation | Edward M. McCombs, Daniel C. Chow, Alexander E. Runas | 2013-10-29 |
| 8553472 | Memory with a shared I/O including an output data latch having an integrated clamp | Edward M. McCombs, Daniel C. Chow, Alexander E. Runas | 2013-10-08 |
| 5956336 | Apparatus and method for concurrent search content addressable memory circuit | Jon A. Loschke, Charley Michael Parks, Mark D. Franklin | 1999-09-21 |
| 5802586 | Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor | Mark D. Bader, Arthur David Kahlich | 1998-09-01 |
| 5677917 | Integrated circuit memory using fusible links in a scan chain | Richard A. Wheelus, Todd David Haverkos | 1997-10-14 |
| 5610543 | Delay locked loop for detecting the phase difference of two signals having different frequencies | Ray L. Chang, Stephen T. Flannagan | 1997-03-11 |
| 5485110 | ECL differential multiplexing circuit | Stephen T. Flannagan | 1996-01-16 |
| 5477176 | Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory | Ray L. Chang, Lawrence F. Childs, Donovan Raatz, Stephen T. Flannagan | 1995-12-19 |
| 5473561 | BICMOS cache TAG having ECL reduction circuit with CMOS output | Mark D. Bader, Ketan B. Shah | 1995-12-05 |
| 5440515 | Delay locked loop for detecting the phase difference of two signals having different frequencies | Ray L. Chang, Stephen T. Flannagan | 1995-08-08 |
| 5422848 | ECL-to-CMOS buffer having a single-sided delay | Ray L. Chang | 1995-06-06 |
| 5402389 | Synchronous memory having parallel output data paths | Stephen T. Flannagan, Roger I. Kung | 1995-03-28 |
| 5400274 | Memory having looped global data lines for propagation delay matching | Lawrence F. Childs | 1995-03-21 |
| 5384737 | Pipelined memory having synchronous and asynchronous operating modes | Lawrence F. Childs, Stephen T. Flannagan, Ray L. Chang | 1995-01-24 |
| 5268863 | Memory having a write enable controlled word line | Mark D. Bader, Karl L. Wang, Ray L. Chang | 1993-12-07 |
| 5258951 | Memory having output buffer enable by level comparison and method therefor | Ruey J. Yu, Ray L. Chang, Karl L. Wang | 1993-11-02 |