Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11226821 | Computer processor employing operand data with associated meta-data | Roger Rawson Godard, David Arthur Yost, Sebastien Paul Maurice Mirolo | 2022-01-18 |
| 10802987 | Computer processor employing cache memory storing backless cache lines | Roger Rawson Godard | 2020-10-13 |
| 10678700 | CPU security mechanisms employing thread-specific protection domains | Roger Rawson Godard, Jan Schukat, William Scott Edwards | 2020-06-09 |
| 9965274 | Computer processor employing bypass network using result tags for routing result operands | Roger Rawson Godard | 2018-05-08 |
| 9959119 | Computer processor employing double-ended instruction decoding | Roger Rawson Godard, David Arthur Yost | 2018-05-01 |
| 9875106 | Computer processor employing instruction block exit prediction | Roger Rawson Godard | 2018-01-23 |
| 9817669 | Computer processor employing explicit operations that support execution of software pipelined loops and a compiler that utilizes such operations for scheduling software pipelined loops | Roger Rawson Godard, David Arthur Yost | 2017-11-14 |
| 9785441 | Computer processor employing instructions with elided nop operations | Roger Rawson Godard, David Arthur Yost | 2017-10-10 |
| 9747218 | CPU security mechanisms employing thread-specific protection domains | Roger Rawson Godard, Jan Schukat | 2017-08-29 |
| 9747216 | Computer processor employing byte-addressable dedicated memory for operand storage | Roger Rawson Godard, Sebastien Paul Maurice Mirolo, David Arthur Yost | 2017-08-29 |
| 9747238 | Computer processor employing split crossbar circuit for operand routing and slot-based organization of functional units | Roger Rawson Godard, Sebastien Paul Maurice Mirolo, David Arthur Yost | 2017-08-29 |
| 9690581 | Computer processor with deferred operations | Roger Rawson Godard, Nachum M. Kanovsky, David Arthur Yost, Sebastien Paul Maurice Mirolo | 2017-06-27 |
| 9652230 | Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache lines | Roger Rawson Godard, Norman Hardy, Allen J. Baum | 2017-05-16 |
| 9524163 | Computer processor employing hardware-based pointer processing | Roger Rawson Godard | 2016-12-20 |
| 9513920 | Computer processor employing split-stream encoding | Roger Rawson Godard, David Arthur Yost | 2016-12-06 |
| 9513904 | Computer processor employing cache memory with per-byte valid bits | Roger Rawson Godard | 2016-12-06 |
| 9513921 | Computer processor employing temporal addressing for storage of transient operands | Roger Rawson Godard, Sebastien Paul Maurice Mirolo, David Arthur Yost | 2016-12-06 |
| 5802586 | Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor | Kenneth W. Jones, Mark D. Bader | 1998-09-01 |