Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8059441 | Memory array on more than one die | Mohammed H. Taufique, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II +2 more | 2011-11-15 |
| 7692946 | Memory array on more than one die | Mohammed H. Taufique, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II +2 more | 2010-04-06 |
| 6285580 | Method and apparatus for hardening a static random access memory cell from single event upsets | Ho Gia Phan, Bin Li, Joseph A. Hoffman | 2001-09-04 |
| 6275080 | Enhanced single event upset immune latch circuit | Ho Gia Phan, Bin Li | 2001-08-14 |
| 6208554 | Single event upset (SEU) hardened static random access memory cell | Ho Gia Phan, Bin Li, Joseph A. Hoffman | 2001-03-27 |
| 5592426 | Extended segmented precharge architecture | Christopher M. Durham, Michael K. Ciraula | 1997-01-07 |
| 5301165 | Chip select speedup circuit for a memory | Michael K. Ciraula, Christopher M. Durham | 1994-04-05 |
| 5146111 | Glitch-proof powered-down on chip receiver with non-overlapping outputs | Michael K. Ciraula, Christopher M. Durham | 1992-09-08 |
| 5117129 | CMOS off chip driver for fault tolerant cold sparing | Joseph A. Hoffman, Yogishwar K. Puri, Randall Richards | 1992-05-26 |
| 4996670 | Zero standby power, radiation hardened, memory redundancy circuit | Michael K. Ciraula, Christopher M. Durham | 1991-02-26 |